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參數(shù)資料
| 型號： | TB31356AFL |
| 廠商： | Toshiba Corporation |
| 英文描述： | 1.8GHz,600MHz DUAL-PLL FREQUENCY SYNTHESIZER |
| 中文描述： | 配備1.8GHz，600MHz的雙鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 297K |
| 代理商： | TB31356AFL |
TENTATIVE TB31356AFL
DESCRIPTION OF FUNCTION AND OPERATION
This specification is design target. It is subject to change without notice
.
Nov. 27 2002 PAGE 4
(1) Serial data control
TB31356AFL operates according to serial data program. Serial data is input from the clock (CLK),
data (DATA), and strobe (STB) pin.
(2) Entry of serial data
l
At the rising edge of each clock pulse, data is sent to the internal shift register from the LSB
sequentially. When all the data is sent, set the strobe pin to high. At this rising edge,
data is stored in latches depending on the control contents. At the same time as data is
stored, control starts.
l
The CLK, DATA, and STB pin contain the schmitt trigger circuit to prevent the data
errors by noise, etc.
At power on, send the option control data before any other divider data.
l
(3) Serial data input timing
(4) Serial data groups and group code
l
The IC has control divided into five groups so that they may be controlled independent of
one another. Each group is identified by three-bit group code attached at the data end.
Bit before
preceding one
Preceding bit
Last bit
Control contents
0
0
0
PLL1 programmable divider (FIN1) data
0
1
0
PLL2 programmable divider (FIN2) data
0
0
1
PLL1 reference divider (XIN) data
0
1
1
PLL2 reference divider (XIN) data
1
0
0
Option Control
CLK
DATA
STB
=>0.1
μ
s
=>0.04
μ
s
=>0.04
μ
s
=>0.02
μ
s
=>0.02
μ
s
=>0.04
μ
s
=>0.04
μ
s
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