- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383878 > TAS5036A (Texas Instruments, Inc.) Six Channel Digital Audio PWM Processor PDF資料下載
參數(shù)資料
| 型號： | TAS5036A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Six Channel Digital Audio PWM Processor |
| 中文描述： | 六通道數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 21/62頁 |
| 文件大?。?/td> | 790K |
| 代理商： | TAS5036A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁
Architecture Overview
15
SLES061B—November 2002—Revised January 2004
TAS5036A
2.1.7.4
DSP Mode Timing
DSP mode timing uses LRCLK to define when data is to be transmitted for both channels. A bit clock running
at 64
×
Fs is used to clock in the data. The first bit of the left channel data appears on the data lines following
the LRCLK transition. The data is written MSB first and is valid on the rising edge of the bit clock. The
TAS5036A masks unused trailing data bit positions.
SCLK
LRCLK
64 SCLKS
LSB
MSB
16 Bits
Left
Channel
16 Bits
Right
Channel
32 Bits Unused
SDIN
LSB
MSB
Figure 29. DSP Format
2.2
Reset, Power Down, and Status
The reset, power down, and status circuitry provides the necessary controls to bring the TAS5036A to the initial
inactive condition, achieve low-power standby, and report system status.
2.2.1 Reset—RESET
The TAS5036A is placed in the reset mode by setting the RESET terminal low.
RESET is an asynchronous control signal that restores the TAS5036A to its default conditions, sets the valid
16 outputs low, and places the PWM in the hard mute state. Volume is immediately set to full attenuation
(there is no ramp down).
As long as the RESET terminal is held low, the device is in the reset state. During reset, all I
2
C and serial data
bus operations are ignored. Table 26 shows the device output signals while RESET is active.
Upon the release of RESET, if POWER_DWN is high, the system performs a 4-ms to 5-ms device initialization
and then ramps the volume up to 0 db using a soft volume update sequence. If MCLK_IN is not active when
RESET is released high, then a 4-ms to 5-ms initialization sequence is produced once MCLK_IN becomes
active.
During device initialization all controls are reset to their initial states. Table 27 shows the control settings that
are changed during initialization.
RESET should be applied during power-up initialization or while changing the master slave clock states.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TAS5036A_06 | Six Channel Digital Audio PWM Processor |
| TAS5036AIPFC | Six Channel Digital Audio PWM Processor |
| TAS5036AIPFCG4 | Six Channel Digital Audio PWM Processor |
| TAS5036AIPFCR | Six Channel Digital Audio PWM Processor |
| TAS5036AIPFCRG4 | Six Channel Digital Audio PWM Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5036A_06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Six Channel Digital Audio PWM Processor |
| TAS5036AIPFC | 功能描述:音頻放大器 Digital Audio PWM Processor RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5036AIPFCG4 | 功能描述:音頻放大器 Digital Audio PWM Processor RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5036AIPFCR | 功能描述:音頻放大器 Digital Audio PWM Processor RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TAS5036AIPFCRG4 | 功能描述:音頻放大器 Digital Audio PWM Processor RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。