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參數(shù)資料
| 型號： | TAS5010IPFBRG4 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TRUE DIGITAL AUDIO AMPLIFIER DIGITAL AUDIO PWM PROCESSOR |
| 中文描述： | 真正的數(shù)字音頻放大器，數(shù)字音頻PWM處理器 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 268K |
| 代理商： | TAS5010IPFBRG4 |
TAS5010
SLAS328
–
SEPTEMBER 2001
4
www.ti.com
Terminal Functions
TERMINAL
NAME
AVDD1
AVDD2
AVSS1
AVSS2
DBSPD
DEM_EN
DEM_SEL
DVDD1
DVDD2
DVDD3_L
DVDD3_R
DVSS1
DVSS2
DVSS3_L
DVSS3_R
FTEST
LRCLK
MCLK_IN
MCLK_OUT
MOD0
MOD1
MOD2
M_S
MUTE
NC
I/O
DESCRIPTION
NO.
48
2
44
5
39
43
42
12, 14
31
36
25
13, 15
30
37
24
41
18
1
16
22
21
20
10
38
6, 11, 26,
27, 32, 33
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog supply for oscillator
Analog supply for PLL
Analog ground for oscillator
Analog ground for PLL
Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high
De-emphasis enable, active high
De-emphasis select (0 = 44.1 kHz, 1 = 48 kHz)
Digital voltage supply for logic
Digital voltage supply for PWM reclocking
Digital voltage supply for PWM output (left)
Digital voltage supply for PWM output (right)
Digital ground for logic
Digital ground for PWM reclocking
Digital ground for PWM output (left)
Digital ground for PWM output (right)
Tied to DVSS1 for normal operation
Left/right clock (input when M_S = 0; output when M_S = 1)
MCLK input
Buffered system clock output if M_S = 1; otherwise set to 0
Serial interface selection pin, bit 0
Serial interface selection pin, bit 1
Serial interface selection pin, bit 2 (MSB)
Master/slave, master=1, slave=0
Muted signal = 0, normal mode = 1
No connection
I/O
I
O
I
I
I
I
I
OSC_CAP
PDN
PLL_FLT_OUT
PLL_FLT_RET
PWM_AM_L
PWM_AM_R
PWM_AP_L
PWM_AP_R
RESET
SCLK
SDIN
STEST
VALID_L
VALID_R
XTL_IN
XTL_OUT
45
8
3
4
34
28
35
29
7
17
19
40
23
9
47
46
I
I
Oscillator cap return
Power down, active low
Output terminal for external PLL filter
Return for external PLL filter
PWM left output (differential
–
)
PWM right output (differential
–
)
PWM left output (differential +)
PWM right output (differential +)
Reset (active low)
Shift clock (input when M_S = 0, output when M_S = 1)
Stereo serial audio data input
Tied to DVSS1 for normal operation
PWM left outputs valid (active high)
PWM right outputs valid (active high)
Crystal or clock input (MCLK input)
Crystal output (not for external usage).NC when XTL_IN is MCLK input
O
I
O
O
O
O
I
I/O
I
I
O
O
I
O
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| TAS5028A | 8 Channel Digital Audio PWM Processor |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TAS5010PFB | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5010PFBG4 | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5010PFBR | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5010PFBRG4 | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5012 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:TRUE DIGITAL AUDIO AMPLIFIER TAS5012 DIGITAL AUDIO PWM PROCESSOR |
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