參數(shù)資料
型號: T83C5101ZZZ-3ZSIL
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP24
封裝: DIP-24
文件頁數(shù): 33/52頁
文件大小: 701K
代理商: T83C5101ZZZ-3ZSIL
Rev. F - 12 March, 2001
39
T87C5101
T83C5101/02
Figure 15. Programming / Verifying signals’waveform
Note: after programming, addresses high and low are already latched in the device, and when switching to verify,
the device outputs directly the last written data.
12 MHz
Symbol
Parameter
Formula
Min
Max
Unit
tOSC
Oscillator period
-
83.3
ns
tCVPX
Code input Valid to Vpp rising edge setup time
36 tOSC
3
s
tPHCX
Code input valid from Vpp High hold time
1 tOSC
83.3
ns
tPHTX
Test input valid from Vpp High hold time
1 tOSC
83.3
ns
tTHTX
Test High pulse width
36 tOSC
3
s
tCVTX
Address high Valid to Test falling edge setup time
36 tOSC
3
s
tTLCX
Address input Valid from Test falling edge hold time
1 tOSC
83.3
ns
tPHDZ
Data output Hi-Z from Vpp high delay
0
tGLGX
Prog Low pulse width
90
110
s
tCVGX
Address valid to Prog falling edge setup time
36 tOSC
3
s
tDVGX
Data input Valid to Prog falling edge setup time
36 tOSC
3
s
tGHCX
Address valid from Prog rising edge hold time
1 tOSC
83.3
ns
tGHDX
Data input valid from Prog High hold time
1 tOSC
83.3
ns
tGHPX
Vpp on Vpp pin from Prog High hold time
36 tOSC
3
s
tTXDX
Data output valid from T code invalid hold time
0
tTVDV
Data output valid from T code valid delay
36 tOSC
3
s
tPLCX
Address valid from Vpp falling edge hold time
36 tOSC
3
s
tPPGX
Vpp on Vpp pin to Prog falling edge setup time
36 tOSC
3
s
tPLDX
Data output from Vpp Low delay
0
s
tPLCX
tPHDZ
tGLGX
tGHDX
tGHCX
tDVGX
tCVGX
tTLCX
tCVTX
tTHTX
tPPGX
tCVPX
tGHPX
tPHTX
tPHCX
TCode Prog
ADH#1
ADL#1
Data#1 (in)
TCode Ver
TCode Prog
ADL#2
Data#2 (in)
Vpp
TEST
PROG
P3
P1
Vpp=12.75V
Data#1 (out)
tTVDV
tTXDX
tPLDX
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