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| 型號： | T83C5101ZZZ-3ZSIL |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PDIP24 |
| 封裝： | DIP-24 |
| 文件頁數(shù)： | 19/52頁 |
| 文件大小： | 701K |
| 代理商： | T83C5101ZZZ-3ZSIL |
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26
Rev. F - 12 March, 2001
T87C5101
T83C5101/02
7.6. Interrupt System
The T8xC5101/02 family has a total of 6 interrupt vectors: two external interrupts (INT0 and INT1), three timer
interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 10. The addresses
of the interrupt vectors are the same as in the standard C52.
Figure 10. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 10.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 11.) and in the Interrupt Priority High register (See Table 12.).
shows the bit values and priority levels associated with each combination.
Table 9. Priority Level Bit Values
IPH.x
IP.x
Interrupt Level Priority
0
0 (Lowest)
0
1
0
2
1
3 (Highest)
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing
from high to low priority
Low priority
interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IP
IE0
0
3
0
3
0
3
0
3
0
3
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