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參數資料
| 型號： | T7570 |
| 廠商： | Lineage Power |
| 元件分類： | Codec |
| 英文描述： | Programmable PCM Codec with Hybrid-Balance Filter(帶混合平衡濾波器的可編程PCM編解碼器) |
| 中文描述： | 可編程PCM編解碼器與混合平衡濾波器（帶混合平衡濾波器的可編程的PCM編解碼器） |
| 文件頁數： | 20/28頁 |
| 文件大?。?/td> | 489K |
| 代理商： | T7570 |
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20
Lucent Technologies Inc.
T7570 Programmable PCM Codec
with Hybrid-Balance Filter
Data Sheet
October 1996
Timing Characteristics
A signal is valid if it is above V
IH
or below V
IL
and invalid if it is between V
IL
and V
IH
. For the purposes of this specifi-
cation, the following conditions apply:
I
All input signals are defined as V
IL
= 0.4 V, V
IH
= 2.7 V, t
R
< 10 ns, t
F
< 10 ns.
I
t
R
is measured from V
IL
to V
IH
. t
F
is measured from V
IH
to V
IL
.
I
Delay times are measured from the input signal valid to the output signal valid.
I
Setup times are measured from the data input valid to the clock input invalid.
I
Hold times are measured from the clock signal valid to the data input invalid.
I
Pulse widths are measured from V
IL
to V
IL
or from V
IH
to V
IH
.
Table 19. Master Clock Timing
(See Figures 4 and 5.)
Symbol
fMCLK
Parameter
Test Conditions
—
Min
—
—
—
—
80
80
—
—
50
Typ
1536
1544
2048
4096
—
—
—
—
—
Max
—
—
—
—
—
—
30
30
—
Unit
kHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
Frequency of MCLK—Selection
Frequency Is Programmable
(See Table 3.)
tMCHMCL
tMCLMCH
tMCH1MCH2 Rise Time of MCLK
tMCL2MCL1
Fall Time of MCLK
tBCLMCH
Hold Time, BCLK Low to MCLK
High
tFSLFSH
Period of FS
X
or FS
R
Low
Time of MCLK High
Time of MCLK Low
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
—
Measured from V
IL
to V
IL
1
—
—
MCLK
Period
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