參數(shù)資料
型號(hào)： T520X477M006SE018
廠商： Texas Instruments, Inc.
英文描述： 60-A, 3.3/5-V INPUT, NONISOLATED WIDE-OUTPUT ADJUST POWER MODULE
中文描述： 60甲，3.3/5-V輸入，非隔離寬輸出調(diào)節(jié)電源模塊
文件頁(yè)數(shù)： 3/24頁(yè)
文件大?。?/td> 947K
代理商： T520X477M006SE018
www.ti.com
ELECTRICAL CHARACTERISTICS
T
A
= 25
°
C, V
I
= 5 V, V
O
= 2.5 V, C
I
= 1000 μF, C
O
= 660 μF, and I
O
= I
O
max (unless otherwise stated)
PTH04040W
SLTS238A–SEPTEMBER 2005–REVISED FEBRUARY 2006
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
O
V
I
V
O
tol
Reg
temp
Reg
line
Reg
load
Reg
tot
Output current
60
°
C, 200 LFM airflow
Over I
O
range
0
60
(1)
A
Input voltage range
2.95
5.5
V
Set-point voltage tolerance
±
2
(3)
%V
O
%V
O
mV
Temperature variation
–40
°
C < T
A
< 85
°
C
Over V
I
range
Over I
O
range
Includes set-point, line, load, –40
°
C
≤
T
A
≤
85
°
C
±
0.5
±
5
±
5
Line regulation
Load regulation
mV
Total output variation
±
3
(3)
1.65
%V
O
2.95
≤
V
I
≤
4.5 V
(3)
4.5
≤
V
I
≤
5.5 V
(3)
R
SET
= 2.21 k
, V
O
= 2.5 V
R
SET
= 5.49 k
, V
O
= 1.8 V
R
SET
= 8.87 k
, V
O
= 1.5 V
R
SET
= 17.4 k
, V
O
= 1.2 V
R
SET
= 6.92 k
, V
O
= 1.65 V
R
SET
= 8.87 k
, V
O
= 1.5 V
R
SET
= 36.5 k
, V
O
= 1 V
0.8
-
V
O, ADJ
Output adjust range
V
0.8
-
2.5
93%
90%
V
I
= 5 V, I
O
= 45 A
88%
η
Efficiency
86%
92%
V
I
= 3.3 V, I
O
= 45 A
91%
87%
V
R
I
O
trip
V
O
ripple (peak-to-peak)
Overcurrent threshold
20-MHz bandwidth
All voltages
15
mV
PP
A
Reset, followed by auto-recovery
90
Transient response
1 A/μs load step, 50 to 100% I
O
max, C
O
= 660 μF
t
rr
V
tr
Recovery time
100
μS
V
O
over/undershoot
200
mV
Margin up down adjust
From a given set-point voltage
±
5%
–8
(4)
%
I
IL
margin
I
IL
track
dV/dt
Margin input current
Pin to GND
μA
Track input current (pin 18)
Pin to GND
–0.11
(5)
mA
Track slew rate capability
|V
TRACK
– V
O
|
≤
50 mV and V
(TRACK)
< V
O
(nom)
Pin 8 open
1
V/ms
UVLO
Undervoltage lockout
On-threshold
2.6
(6)
V
Hysterisis
0.6
(6)
Inhibit control (pin 7)
Referenced to GND
V
IH
V
IL
I
IL
inhibit
I
I
inh
f
s
C
I
Input high voltage
2.5
Open
(5)
V
Input low voltage
–0.2
0.5
Input low current
Pin to GND
0.5
mA
Input standby current
Inhibit (pin 7) to GND
60
mA
Switching frequency
Over V
I
and I
O
ranges
675
825
975
kHz
External input capacitance
940
(7)
μF
(1)
(2)
See SOA curves or consult factory for appropriate derating.
The nominal input voltage must be at least 2
×
V
. Output voltage regulation is guaranteed with an input voltage within
±
10% from
nominal 3.3 V or 5 V. For example, for V
= 5 V and V
= 2.5 V, the input can vary between 4.5 V and 5.5 V.
The set-point voltage tolerance is affected by the tolerance of R
SET
. The stated limit is unconditionally met if R
SET
has a tolerance of 1%
with 100 ppm/
°
C or better temperature stability.
A small, low-leakage (<100 nA) MOSFET is recommended to control this pin. The open-circuit voltage is less than 1 Vdc.
This control pin has an internal pull-up to V
. If it is left open-circuit the module operates when input power is applied. A small,
low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is recommended for control. Do not place an external
pull-up on this pin. See the
Application Information
section for further guidance.
These are the default voltages. They may be adjusted using the
UVLO Prog
control input. See the
Application Information
section for
further guidance.
A minimum capacitance of 940
μ
F is required at the input for proper operation. The capacitance must be rated for a minimum of 400
mArms of ripple current.
(3)
(4)
(5)
(6)
(7)
3
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