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參數(shù)資料
| 型號(hào)： | T520X477M006SE018 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 60-A, 3.3/5-V INPUT, NONISOLATED WIDE-OUTPUT ADJUST POWER MODULE |
| 中文描述： | 60甲，3.3/5-V輸入，非隔離寬輸出調(diào)節(jié)電源模塊 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 947K |
| 代理商： | T520X477M006SE018 |
www.ti.com
t Time 20 ms/div
V
TRK
(1 V/div)
V
0
1 (1 V/div)
V
0
2 (1 V/div)
t Time 200
μ
s/div
V
TRK
(1 V/div)
V
0
1 (1 V/div)
V
0
2 (1 V/div)
MARGIN UP/DOWN CONTROLS
D
%
R
orR
=
U
D
499
-99.8k
W
(4)
PTH04040W
SLTS238A–SEPTEMBER 2005–REVISED FEBRUARY 2006
Figure 16. Auto-Track Simultaneous Power Up
Waveforms
Figure 17. Auto-Track Simultaneous Power Down
Waveforms
The PTHxx060, PTHxx010, PTHxx020, and PTHxx030 products incorporate
Margin Up
and
Margin Down
control
inputs. These controls allow the output voltage to be momentarily adjusted
(1)
, either up or down, by a nominal
5%. This provides a convenient method for dynamically testing the operation of the load circuit over its supply
margin or range. It can also be used to verify the function of supply voltage supervisors. The
±
5% change is
applied to the adjusted output voltage, as set by the external resistor, R
set
at the
V
o
Adjust
pin.
The 5% adjustment is made by pulling the appropriate margin control input directly to the GND terminal 2. A
low-leakage open-drain device, such as an n-channel MOSFET or p-channel JFET is recommended for this
purpose
(3)
. Adjustments of less than 5% can also be accommodated by adding series resistors to the control
inputs. The value of the resistor can be selected from
Table 4
, or calculated using the following formula.
UP/DOWN ADJUST RESISTANCE CALCULATION
Where
% = The desired amount of margin adjusted in percent.
NOTES
1. The
Margin Up
and
Margin Down
controls were not intended to be activated simultaneously. If they are
activated simultaneously, the effects on the output voltage may not completely cancel, resulting in the
possibility of a higher error in the output voltage set point.
2. The ground reference should be a direct connection to the module
GND
at pin 7 (pin 1 for the PTHxx050).
This produces a more accurate adjustment at the load circuit terminals. The transistors Q1 and Q2 should be
located close to the regulator.
3. The Margin Up and Margin Down control inputs are not compatible with devices that source voltage. This
includes TTL logic. These are analog inputs and should only be controlled with a true open-drain device
(preferably discrete MOSFET transistor). The device selected should have low off-state leakage current.
Each input sources 8 μA when grounded, and has an open-circuit voltage of 0.8 V.
19
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