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參數(shù)資料
| 型號： | SYM53C860 |
| 廠商： | LSI Corporation |
| 英文描述： | Single-Chip High-Performance PCI-Ultra SCSI (Fast-20) I/O Processor(單片、高性能PCI-超級SCSI (Fast-20) I/O 處理器) |
| 中文描述： | 單芯片高性能的PCI -超的SCSI（快速- 20）I / O處理器（單片，高性能的PCI -超級的SCSI（快速- 20）的I / O處理器） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 38K |
| 代理商： | SYM53C860 |
7
Bit 15 PME Status (PST)
The device always returns a 0 for this bit, indicating that PME signal generation is not sup-
ported from D3cold.
Bits 14-13 Data Scale (DSCL)
The device does not support the Data register, therefore this field is always set to 00b.
Bits 12-9 Data Select (DSLT)
The device does not support the Data register, therefore this field is always set to 0000b
.
Bit 8 PME Enable (PEN)
The device always returns a 0 for this bit to indicate that PME assertion is disabled.
Bits 7-2 Reserved
Bits 1-0 Power State (PWS)
This two bit field determines the current power state for the function and is used to set the
function to a new power state. The definitions of the field values are:
00b - D0
01b - Reserved
10b - Reserved
11b - D3hot
Register 46h
PMCSR BSE
Read Only
BSE
7
Default >>>
0
BSE
6
BSE
5
BSE
BSE
BSE
BSE
BSE
4
3
2
1
0
0
0
0
0
0
0
0
This register can support PCI bridge specific functionality if required. The default value always
returns 00h.
Register 47h
Data
Read Only
This register provides an optional mechanism for the function to report state-dependent operating
data. The default value is 00h.
This is currently not implemented for these devices.
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