- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385894 > SYM53C141 (LSI CORP) SCSI Bus Expander(SCSI總線擴展器) PDF資料下載
參數(shù)資料
| 型號： | SYM53C141 |
| 廠商： | LSI CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SCSI Bus Expander(SCSI總線擴展器) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, QFP-128 |
| 文件頁數(shù)： | 26/68頁 |
| 文件大?。?/td> | 630K |
| 代理商： | SYM53C141 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
2-8
Functional Description
A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
2.7.3 Request (REQ)/Acknowledge (ACK) Control
A_SACK/, B_SACK
±
, A_SREQ/ and B_SREQ
±
are clock and control
signals. Their signal paths contain controls to guarantee minimum pulse
width, filter edges, and does some re-timing when used as data transfer
clocks. Each signal, REQ and ACK, has paths from A to B and B to A.
The received signal goes through the following processing steps before
being sent to the opposite bus.
1.
The asserted input signal is sensed and forwarded to the next stage
if the direction control permits it. The direction controls are developed
from state machines that are driven by the sequence of bus control
signals.
2.
The signal must then pass the test of not being generated by the
SYM53C141.
3.
In the A to B bus direction, the next stage is a leading edge filter.
This ensures that the output does not switch during the specified
hold time after the leading edge. The duration of the input signal
determines the duration of the output after the hold time. In the B to
A direction, the circuit guarantees a minimum pulse.
4.
The next stage passes the signal if it is not a data clock. If REQ or
ACK is a data clock, it delays the leading edge to improve data
output setup times. The duration is again controlled by the input
signal.
5.
The following stage is a trailing edge signal filter. When the signal
deasserts, the filter does not permit any signal bounce. The output
signal deasserts at the first deasserted edge of the input signal.
6.
The last stage develops pull-up and pull-down signals with drive and
3-state control.
7.
A parallel function ensures that bus (transmission line) recovery is
ensured for a specified time after the last signal deassertion on each
signal line.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SYM53C180 | Ultra3 SCSI Bus Expander(Ultra2 SCSI總線擴展器) |
| SYM53C710 | 32-Bit SCSI I/O Processor(32位SCSI I/O處理器) |
| SYM53C770 | SCSI I/O Processor With Ultra SCSI(帶超級SCSI的SCSI I/O處理器) |
| SYM53C810A | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
| SYM53C825A | PCI-SCSI I/O Processor(PCI-SCSI I/O接口處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SYM53C400A | 制造商:SYMBIOS 功能描述: |
| SYM53C770 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C876E(PQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SCSI Bus Interface/Controller |
| SYM53C885 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。