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參數(shù)資料
| 型號(hào)： | SY100S834L |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | （÷1，÷2，÷4）or（÷2，÷4，÷8）Clock Generation Chip(低斜移（÷1，÷2，÷4）或（÷2，÷4，÷8）時(shí)鐘發(fā)生芯片) |
| 中文描述： | （÷ 1，÷ 2，÷ 4）或（÷ 2，÷ 4，÷ 8）時(shí)鐘發(fā)生器芯片（低斜移（÷ 1，÷ 2，÷ 4）或（÷ 2，÷ 4，÷ 8）時(shí)鐘發(fā)生芯片） |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 67K |
| 代理商： | SY100S834L |
The SY100S834/L is low skew (
÷
1,
÷
2,
÷
4) or (
÷
2,
÷
4,
÷
8) clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the V
BB
output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the V
BB
output should be connected
to the CLK input and bypassed to ground via a 0.01
μ
F
capacitor. The V
BB
output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
The Function Select (F
SEL
) input is used to determine
what clock generation chip function is. When FS
EL
input
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FS
EL
input
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
DESCRIPTION
I
3.3V and 5V power supply options
I
50ps output-to-output skew
I
Synchronous enable/disable
I
Master Reset for synchronization
I
Internal 75K
input pull-down resistors
I
Available in 16-pin SOIC package
FEATURES
Rev.: F
Issue Date: September, 1999
Amendment: /0
(
÷
1,
÷
2,
÷
4) OR (
÷
2,
÷
4,
÷
8)
CLOCK GENERATION CHIP
ClockWorks
SY100S834
SY100S834L
Pin
Function
CLK
Differential Clock Inputs
F
SEL
Function Select
EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0
Differential
÷
1 or
÷
2 Outputs
Differential
÷
2 or
÷
4 Outputs
Differential
÷
4 or
÷
8 Outputs
Q
1
Q
2
PIN NAMES
CLK
EN
MR
Function
Z
L
L
Divide
ZZ
H
L
Hold Q
0–2
X
X
H
Reset Q
0–2
NOTES:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
TRUTH TABLE
F
SEL
L
Q
0
Outputs
Divide by 2
Q
1
Outputs
Divide by 4
Q
2
Outputs
Divide by 8
H
Divide by 1
Divide by 2
Divide by 4
PIN CONFIGURATION/BLOCK DIAGRAM
SOIC
TOP VIEW
V
CC
EN
F
SEL
CLK
CLK
V
BB
MR
V
EE
Q
0
Q
0
V
CC
Q
1
Q
1
V
CC
Q
2
Q
2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
Q
R
Q
R
÷
1 or
÷
2
Q
Q
R
R
D
÷
2 or
÷
4
÷
4 or
÷
8
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100S834LZC | 功能描述:IC CLOCK GEN 3.3V/5V 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| SY100S834LZC TR | 功能描述:IC CLOCK GEN 3.3V/5V 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| SY100S834LZG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V (/1, /2, /4) or (/2, /4, /8) Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY100S834LZG TR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V (/1, /2, /4) or (/2, /4, /8) Clock Generation Chip (I Temp, Green) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SY100S834LZI | 功能描述:IC CLOCK GEN 3.3V/5V 16-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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