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參數(shù)資料
| 型號： | SY100S336AJC |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | ENHANCED 4-STAGE COUNTER/SHIFT REGISTER |
| 中文描述： | 100S SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 149K |
| 代理商： | SY100S336AJC |
Pin
Function
CP
Clock Pulse Input
CEP
Count Enable Parallel Input (Active LOW)
D
0
/CET
Serial Data Input/Count Enable Trickle
Input (Active LOW)
S
0
— S
2
Select Inputs
MR
Master Reset Input
V
EES
V
EE
Substrate
V
CCA
V
CCO
for ECL Outputs
P
0
– P
3
Preset Inputs
D
3
Serial Data Input
TC
Terminal Count Output
Q
0
— Q
3
Data Outputs
Q
0
— Q
3
Complementary Data Outputs
PIN NAMES
SY100S336A
ENHANCED 4-STAGE
COUNTER/SHIFT REGISTER
I
Max. shift frequency of 700MHz
I
Clock to Q delay max. of 1100ps
I
S
n
to TC speed improved by 50%
I
S
n
set-up and hold time reduced by more than 50%
I
I
EE
min. of –170mA
I
Industry standard 100K ECL levels
I
Internal 75K
input pull-down resistors
I
Extended supply voltage option:
V
EE
= –4.2V to –5.5V
I
Voltage and temperature compensation for improved
noise immunity
I
50% faster than Fairchild 300K at lower power
I
Function and pinout compatible with Fairchild F100K
I
Available in 24-pin CERPACK and 28-pin PLCC
packages
FEATURES
DESCRIPTION
The SY100S336A is functionally the same as the
SY100S336, but has S
n
to TC speed and Sn set-up and
hold times significantly improved, allowing for higher clock
frequency when used as a cascaded multi-stage counter.
The SY100S336A functions either as a modulo-16 up/
down counter or as a 4-bit bidirectional shift register and is
designed for use in high-performance ECL systems. Three
Select inputs (Sn) are provided for determining the mode of
operation. The Function Table lists the available modes of
operation. In order to allow cascading for multistage
counters, two Count Enable controls (CEP, CET) are
provided. The CET input also functions as the Serial Data
input (S
0
) for a shift-up operation, while the D
3
input serves
as the Serial Data input for the shift-down operation.
When the device is in the counting mode, the Terminal
Count (TC) goes to a logical LOW when the count reaches
15 for count-up or reaches 0 for count-down. When in the
shift mode, the TC output simply repeats the Q
3
output.
The flexiblity provided by the TC/Q
3
output and the D
0
/
CET input allows these signals to be interconnected from
one stage to the next higher stage for multistage counting
or shift-up operations. The individual Presets (P
n
) allow
initialization of the counter by entering data in parallel to
preset the counter. A logic HIGH on the Master Reset (MR)
overrides all other inputs and asynchronously clears the
flip-flops. An additional synchronous Clear is provided, as
well as a complement function which synchronously inverts
the contents of the flip-flops. All inputs have 75K
pull-
down resistors.
Q
2
Q
2
V
CCA
V
CC
V
CC
Q
1
Q
1
P
0
CP
V
EE
V
EES
MR
S
0
S
1
4
3
2
1
28
27
26
12
13
14
15
16
17
18
19
11
20
10
21
9
22
8
23
7
24
6
Top View
PLCC
J28-1
25
5
P
1
P
2
P
3
V
E
D
3
Q
3
Q
3
D
0
/
V
E
C
T
S
2
Q
0
Q
0
Rev.: G
Issue Date:
Amendment: /0
July, 1999
S
1
S
0
M
V
E
C
P
0
P
1
P
2
P
3
D
3
Q
3
Q
3
S
2
D
0
/CET
Q
0
Q
0
CEP
TC
18
17
16
15
14
13
1
2
3
4
5
6
7
24
8
23
9
22
10
21
11
20
12
19
Top View
Flatpack
F24-1
V
C
V
C
Q
1
Q
2
Q
1
Q
2
PIN CONFIGURATIONS
1
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| SY100S336FC | 功能描述:IC COUNTER/SHIFT REG 24-CERPACK RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100S 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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| SY100S336JC TR | 功能描述:IC COUNTER/SHIFT REG 28-PLCC RoHS:否 類別:集成電路 (IC) >> 邏輯 - 專用邏輯 系列:100S 產(chǎn)品變化通告:Product Discontinuation 25/Apr/2012 標準包裝:1,500 系列:74SSTV 邏輯類型:DDR 的寄存緩沖器 電源電壓:2.3 V ~ 2.7 V 位數(shù):14 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:48-TSSOP 包裝:帶卷 (TR) |
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