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參數(shù)資料
| 型號： | SY100S839VZC |
| 廠商： | MICREL INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | ±2/4, ±4/5/6 CLOCK GENERATION CHIP |
| 中文描述： | 100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 68K |
| 代理商： | SY100S839VZC |
CLK
/EN
MR
Function
Z
L
L
Divide
ZZ
H
L
Hold Q
0–3
X
X
H
Reset Q
0–3
The SY100S839V is a low skew
÷
2/4,
÷
4/5/6 clock
generation chip designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The device can be driven
by either a differential or single-ended ECL/LVECL or, if
positive power supplies are used, PECL/LVPECL input
signal. In addition, by using the V
BB
output, a sinusoidal
source can be AC-coupled into the device. If a single-
ended input is to be used, the V
BB
output should be
connected to the /CLK input and bypassed to ground via
a 0.01
μ
F capacitor. The V
BB
output is designed to act as
the switching reference for the input of the S839V under
single-ended input conditions. As a result, this pin can
only source/sink up to 0.5mA of current.
The common enable (/EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a
random state; the master reset (MR) input must be
asserted to ensure synchronization. For systems which
only use one S839V, the MR pin need not be exercised
as the internal divider designs ensures synchronization
between the
÷
2/4, and the
÷
4/5/6 outputs of a single
device.
PIN CONFIGURATION/BLOCK DIAGRAM
I
3.3V and 5V power supply option
I
50ps output-to-output skew
I
50% duty cycle outputs
I
Synchronous enable/disable
I
Master Reset for synchronization
I
Internal 75K
input pull-down resistors
I
Available in 20-pin SOIC package
TRUTH TABLE
DESCRIPTION
FEATURES
Rev.: A
Issue Date: May, 1999
Amendment: /0
÷
2/4,
÷
4/5/6 CLOCK
GENERATION CHIP
NOTE:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
ClockWorks
SY100S839V
FINAL
Pin
Function
CLK
Differential Clock Inputs
/EN
Synchronous Enable
MR
Master Reset
V
BB
Reference Output
Q
0,
Q
1
Differential
÷
2/4 Outputs
Differential
÷
4/5/6 Outputs
Q
2,
Q
3
DIVSEL
Frequency Select Input
PIN NAMES
DIVSELb1
DIVSELb0
Q
2,
Q
3
OUTPUTS
0
0
Divide by 4
0
1
Divide by 6
1
0
Divide by 5
1
1
Divide by 5
DIVSELa
Q
0,
Q
1
OUTPUTS
0
Divide by 2
1
Divide by 4
V
CC
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
V
EE
V
CC
EN
D
CLK
CLK
V
BB
MR
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
SOIC
Z20-1
D
D
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100S839VZC TR | 功能描述:IC CLOCK GEN 3.3V/5V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| SY100S839VZG | 功能描述:時鐘驅(qū)動器及分配 /2,4, /4,5,6 Clock Divider (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY100S839VZG TR | 功能描述:時鐘驅(qū)動器及分配 /2,4, /4,5,6 Clock Divider (I Temp, Green) RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| SY100S839VZI | 功能描述:IC CLOCK GEN 3.3V/5V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| SY100S839VZI TR | 功能描述:IC CLOCK GEN 3.3V/5V 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:Precision Edge® 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
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