參數(shù)資料
型號: STPCI2HDYC
英文描述: PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述: 周邊(多功能)控制器
文件頁數(shù): 32/71頁
文件大?。?/td> 1071K
代理商: STPCI2HDYC
STRAP OPTION
32/69
Issue 2.4 - February 11, 2002
3.1.3. STRAP REGISTER 2
Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the sta-
tus of pin MD[23]. Bit 4 is writeable, writes to other bits in this register have no effect.
Strap2
Access = 0022h/0023h
Regoffset = 04Ch
7
6
5
4
3
2
1
0
Rsv
MD20
MD19
MD18
MD17
Rsv
This register defaults to the values sampled on MD[23] and MD[20:16] pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-5
Rsv
Reserved.
Bit 4
MD20
This bit reflects the
value sampled on MD[20] pin
and controls the Dot
clock (DCLK) source. Note This bit is writeable as well as readable.
Bit 3
MD19
This bit reflects the
value sampled on MD[19] pin
and controls the
Graphics clock source.
Bit 2
MD18
This bit reflects the
value sampled on MD[18] pin
and controls the
Host/CPU clock source as follows: setting to ’0’: External. HCLK pin is
an input, setting to ’1’: Internal. HCLK pin is an output and is connected
to the internal frequency synthesizer output.
Bit 1
MD17
This bit reflects the
value sampled on MD[17] pin
and controls the PCI
clock output as follows:
Setting to ’0’, the PCI clock output = HCLK / 3
Setting to ’1’, the PCI clock output = HCLK / 2.
Bit 0
Rsv
Reserved.
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