參數(shù)資料
型號(hào)： STPCI2HDYC
英文描述： PERIPHERAL (MULTIFUNCTION) CONTROLLER
中文描述： 周邊（多功能）控制器
文件頁(yè)數(shù)： 20/71頁(yè)
文件大?。?/td> 1071K
代理商： STPCI2HDYC
PIN DESCRIPTION
20/69
Issue 2.4 - February 11, 2002
SOUT1, SOUT2
Serial Output.Data is clocked out
using TCLK/16 (TCLK=BAUD#).
DCD1#, DCD2#
Input Data carrier detect.
RI1#, RI2#
Input Ring indicator.
DSR1#, DSR2#
Input Data set ready.
CTS1#, CTS2#
Input Clear to send.
RTS1#, RTS2#
Output Request to send.
DTR1#, DTR2#
Output Data terminal read.
2.2.9 PARALLEL PORT
(Combined with ISA Bus an IPC)
PE
Paper End.Input status signal from printer.
SLCT
Printer Select. Printer selected input.
BUSY#
Printer Busy.
Input status signal from printer.
ERR#
Error. Input status signal from printer.
ACK#
Acknowledge.
Input status signal from printer.
PDDIR#
Parallel Device Direction.
Bidirectional control line output.
STROBE#
PCS/Strobe#.
Data transfer strobe line to printer.
INIT#
Initialize Printer. This output sends an initial-
ize command to the connected printer.
AUTPFDX#
Automatic Line feed.This output
sends a command to the connected printer to au-
tomatically generate line feed on received car-
riage returns.
SLCTIN#
Select In. Printer select output.
PPD[7-0]
Printer Data Lines Data transfer lines to
printer. Bidirectional depending on modes.
Important Note:
Where the Parallel Port is not used, PPD[0], con-
nected to device pin C25, must be pulled up to ‘1’.
This is to avoid memory access problems associ-
ated with the MCS16 Memory Chip Select line
when in the ISA Bus mode.
2.2.10 PCMCIA INTERFACE
(Combined with PCI / Cardbus)
RESET
Card Reset.This output forces a hard
reset to a PC Card.
A[25:0]
Address Bus. These are the 25 low bits of
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA
bus owns the bus and are outputs at all other
times.
D[15:0]
I/O Data Bus (PCMCIA). These are the
external PCMCIA data bus pins.
CA[25-0]
Card Address. Used with the lower 11
bits of the ISA Address Bus to generate the Card
Address.
IORD#
I/O Read.This output is used with REG# to
gate I/O read data from the PC Card, (only when
REG# is asserted).
IOWR#
I/O Write This output is used with REG#
to gate I/O write data from the PC Card, (only
when REG# is asserted).
WP
Write Protect. This input indicates the status
of the Write Protect switch (if fitted) on memory PC
Cards (asserted when the switch is set to write
protect).
BVD1, BVD2
Battery Voltage Detect. These in-
puts will be generated by memory PC Cards that
include batteries and are an indication of the con-
dition of the batteries. BVD1 and BVD2 are kept
asserted high when the battery is in good condi-
tion.
READY#/BUSY#/IREQ#
Ready/busy/Interrupt re-
quest.This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
WAIT#
Bus Cycle Wait.This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
OE#
Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
WE#/PRGM#
Write Enable. This output is used by
the host for gating Memory Write data. WE# is
also used for memory PC Cards that have pro-
grammable memory.
REG#
Attribute Memory Select. This output is in-
active (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only re-
spond to IORD# or IOWR# when REG# is active
(low). Also see
Section 2.2.6
CD1#, CD2#
Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
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STPCI2HEYI PERIPHERAL (MULTIFUNCTION) CONTROLLER
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STPCINDUSTRIAL 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PC Compatible Embedded Microprocessor
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