參數(shù)資料
型號： STPCI01
英文描述： STPC INDUSTRIAL / PC COMPATIBLE EMBEDED MICROPROCESSOR
中文描述： STPC工業(yè)/ PC兼容的嵌入式微處理器
文件頁數(shù)： 44/71頁
文件大?。?/td> 1071K
代理商： STPCI01
ELECTRICAL SPECIFICATIONS
44/69
Issue 2.4 - February 11, 2002
Figure 4-7 Refresh Cycle (ref table
Table 4-6
)
tCPN
tCPN
tCSR
tRP
tRPC
tRAS
tCHR
tCRS
tCSR
tRP
tRPC
tCRAS
tCCAS
CLK
MA[11:0]
RAS#[3:0]
CAS#[7:0]
Table 4-6. AC Memory Timing Characteristics
Parameter
HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3)
HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3)
HCLK (or GCLK2X) to MA[11:0] bus valid (see Note 3)
HCLK (or GCLK2X) to MWE# valid (see Note 3)
HCLK to MD[63:0] bus valid (see Note 3)
GCLK2X to MD[63:0] bus valid (see Note 3)
MD[63:0] Generic hold
Column Address Hold Time
CAS Hold Time
Data Hold TIme from CAS Low
CAS Precharge Time
CAS to RAS Precharge Time
CAS Low to RAS HIGH (Write only)
CAS Setup Time
Data In Setup Time
Row Address Hold Time
RAS Pulse Width
Random Read or Write Time Cycle
RAS to CAS Delay Time
Note 1; T
Cycle
x n
CAS
+ (t
Data off
- t
CAS out
)
Where T
Cycle
is the number of clock cycles.
n
CAS
is the number of CAS Cycles (see
Section 6.7.
)
T
Dataoff
is the Generic Datahold
t
CAS Out
the CLK (either HCLK or GCLK2X) to CAS Low.
T
Dataoff
and t
CAS Out
are used to refine the timing programming.
Min
Max
17
17
17
17
25
23
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCRAS
tCCAS
tCMA
tCMWE
tCMD
tGCMD
tMDG
tCAH
tCHR
tCOH
tCPN
tCRP
tCRW
tCSR
tDS
tRAH
tRAS
tRC
tRCD
0
≥
1T
Cycles
≥
1T
Cycles
Note 1
1T
Cycles
≤
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
1T
Cycles
≥
3T
Cycles
≥
6T
Cycles
≥
1T
Cycles
Note 2; Value to be derived from CAS pulse width which is programmable (see
Section 6.7.
).
Note 3; for all chronograms, CLK refers to the clock signal that the program is using. It can be either HCLK or GCLK2X
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