參數(shù)資料
型號(hào)： STPCD0112BTC3
元件分類(lèi)： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 7/61頁(yè)
文件大小： 1007K
代理商： STPCD0112BTC3
GENERAL DESCRIPTION
Issue 2.2 - October 13, 2000
7/61
1.GENERAL DESCRIPTION
At the heart of the STPC Client is an advanced
processor block, dubbed the ST X86. The ST X86
includes a powerful x86 processor core along with
a 64-bit DRAM controller, advanced 64bit acceler-
ated graphics and video controller, a high speed
PCI local-bus controller and Industry standard PC
chip set functions (Interrupt controller, DMA Con-
troller, Interval timer and ISA bus) and EIDE con-
troller.
The STPC Client has in addition to the 5ST86 a
Video subsystem and high quality digital Televi-
sion output.
The STMicroelectronics x86 processor core is em-
bedded with standard and application specific pe-
ripheral modules on the same silicon die. The core
has all the functionality of the ST Microelectronics
standard x86 processor products, including the
low power System Management Mode (SMM).
System Management Mode (SMM) provides an
additional interrupt and address space that can be
used for system power management or software
transparent emulation of peripherals. While run-
ning in isolated SMM address space, the SMM in-
terrupt routine can execute without interfering with
the operating system or application programs.
Further power management facilities include a
suspend mode that can be initiated from either
hardware or software. Because of the static nature
of the core, no internal data is lost.
The STPC Client makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main memo-
ry and graphics frame-buffer. This significantly re-
duces total system memory with system perform-
ances equal to that of a comparable solution with
separate frame buffer and system memory. In ad-
dition, memory bandwidth is improved by attach-
ing the graphics engine directly to the 64-bit proc-
essor host interface running at the speed of the
processor bus rather than the traditional PCI bus.
The 64-bit wide memory array provides the sys-
tem with 320MB/s peak bandwidth, double that of
an equivalent system using 32 bits. This allows for
higher screen resolutions and greater colour
depth. The processor bus runs at the speed of the
processor (DX devices) or half the speed (DX2 de-
vices).
The ‘standard’ PC chipset functions (DMA, inter-
rupt controller, timers, power management logic)
are integrated with the x86 processor core.
The PCI bus is the main data communication link
to the STPC Client chip. The STPC Client trans-
lates appropriate host bus I/O and Memory cycles
onto the PCI bus. It also supports the generation
of Configuration cycles on the PCI bus. The STPC
Client, as a PCI bus agent (host bridge class), fully
complies with PCI specification 2.1. The chip-set
also implements the PCI mandatory header regis-
ters in Type 0 PCI configuration space for easy
porting of PCI aware system BIOS. The device
contains a PCI arbitration function for three exter-
nal PCI devices.
The STPC Client integrates an ISA bus controller.
Peripheral modules such as parallel and serial
communications ports, keyboard controllers and
additional ISA devices can be accessed by the
STPC Client chip set through this bus.
An industry standard EIDE (ATA 2) controller is
built into the STPC Client and connected internally
via the PCI bus.
Graphics functions are controlled by the on-chip
SVGA controller and the monitor display is man-
aged by the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations, which include hard-
ware acceleration of text, bitblts, transparent blts
and fills. These operations can operate on off-
screen or on-screen areas. The frame buffer size
is up to 4 MBytes anywhere in the physical main
memory.
The graphics resolution supported is a maximum
of 1280x1024 in 65536 colours at 75Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
STPC Client provides several additional functions
to handle MPEG or similar video streams. The
Video Input Port accepts an encoded digital video
stream in one of a number of industry standard
formats, decodes it, optionally decimates it by a
factor of 2:1, and deposits it into an off screen area
of the frame buffer. An interrupt request can be
generated when an entire field or frame has been
captured.
The video output pipeline incorporates a video-
scaler and colour space converter function and
provisions in the CRT controller to display a video
window. While repainting the screen the CRT con-
troller fetches both the video as well as the normal
non-video frame buffer in two separate internal
FIFOs (256-Bytes each). The video stream can be
colour-space converted (optionally) and smooth
相關(guān)PDF資料
PDF描述
STPCD0113BTC3 32-Bit Microprocessor
STPCI01 STPC INDUSTRIAL / PC COMPATIBLE EMBEDED MICROPROCESSOR
STPCI2 STPC ATLAS DATASHEET / X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS
STPCI2GDYI PERIPHERAL (MULTIFUNCTION) CONTROLLER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
STPCD0113BTC3 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:32-Bit Microprocessor
STPCD0166BTA3 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:PC Compatible Embedded Microprocessor
STPCD0166BTC3 制造商:STMicroelectronics 功能描述:MPU STPC RISC 64-Bit 66MHz 388-Pin BGA
STPCD0166BTI3 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:PC Compatible Embedded Microprocessor
STPCD0175BTC3 功能描述:微處理器 - MPU 75MHz x86 Embedded RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線(xiàn)寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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