參數(shù)資料
型號: STM8L162R8T3
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, LQFP-64
文件頁數(shù): 110/116頁
文件大?。?/td> 1229K
代理商: STM8L162R8T3
STM8L162R8, STM8L162M8
Electrical parameters
Doc ID 17959 Rev 1
9.3.7
Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 41 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 41.
SPI1 characteristics
Symbol
Parameter
Conditions(1)
Min
Max
Unit
fSCK
1/tc(SCK)
SPI1 clock frequency
Master mode
0
8
MHz
Slave mode
0
8
tr(SCK)
tf(SCK)
SPI1 clock rise and fall
time
Capacitive load: C = 30 pF
-
30
ns
tsu(NSS)
(2)
NSS setup time
Slave mode
4 x 1/fSYSCLK
-
th(NSS)
NSS hold time
Slave mode
80
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
105
145
tsu(MI)
tsu(SI)
Data input setup time
Master mode
30
-
Slave mode
3
-
th(MI)
th(SI)
Data input hold time
Master mode
15
-
Slave mode
0
-
ta(SO)
(2)(3)
Data output access time
Slave mode
-
3x 1/fSYSCLK
tdis(SO)
Data output disable time
Slave mode
30
-
tv(SO)
Data output valid time
Slave mode (after enable edge)
-
60
Data output valid time
Master mode (after enable
edge)
-20
th(SO)
Data output hold time
Slave mode (after enable edge)
15
-
Master mode (after enable
edge)
1-
1.
Parameters are given by selecting 10 MHz I/O output frequency.
2.
Values based on design simulation and/or characterization results, and not tested in production.
3.
Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
4.
Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi-Z.
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