參數(shù)資料
型號(hào): STM32F101CBT6XXX
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 36 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件頁(yè)數(shù): 19/81頁(yè)
文件大?。?/td> 988K
代理商: STM32F101CBT6XXX
Pinouts and pin description
STM32F101x8, STM32F101xB
Doc ID 13586 Rev 12
-
86
-
PD5
I/O
FT
PD5
USART2_TX
-
87
-
PD6
I/O
FT
PD6
USART2_RX
-
88
-
PD7
I/O
FT
PD7
USART2_CK
39
55
89
30
PB3
I/O
FT
JTDO
TIM2_CH2 / PB3
TRACESWO
SPI1_SCK
40
56
90
31
PB4
I/O
FT
JNTRST
PB4 / TIM3_CH1
SPI1_MISO
41
57
91
32
PB5
I/O
PB5
I2C1_SMBAl
TIM3_CH2 /
SPI1_MOSI
42
58
92
33
PB6
I/O
FT
PB6
I2C1_SCL(8)/TIM4_CH1 (8)
USART1_TX
43
59
93
34
PB7
I/O
FT
PB7
I2C1_SDA(8)/TIM4_CH2 (8)
USART1_RX
44
60
94
35
BOOT0
I
BOOT0
45
61
95
-
PB8
I/O
FT
PB8
TIM4_CH3 (8)
I2C1_SCL
46
62
96
-
PB9
I/O
FT
PB9
TIM4_CH4 (8)
I2C1_SDA
-
97
-
PE0
I/O
FT
PE0
TIM4_ETR
-
98
-
PE1
I/O
FT
PE1
47
63
99
36
VSS_3
SVSS_3
48
64
100
1
VDD_3
SVDD_3
1.
I = input, O = output, S = supply, HiZ= high impedance.
2.
FT= 5 V tolerant.
3.
Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 2 on page 10.
4.
If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5.
PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6.
Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the
STMicroelectronics website: www.st.com.
7.
The pins number 2 and 3 in the VFQFPN36 package, and 5 and 6 in the LQFP48 and LQFP64 packages are configured as
OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For
the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to
the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8.
This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available
from the STMicroelectronics website: www.st.com.
Table 4.
Medium-density STM32F101xx pin definitions (continued)
Pins
Pin name
Ty
p
e
(1)
I
/O
l
e
vel
(2
)
Main
function(3)
(after reset)
Alternate functions(3)(4)
LQ
FP4
8
LQ
FP6
4
LQ
FP100
VFQFPN36
Default
Remap
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