參數(shù)資料
型號(hào): STM32F101C8T6
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, FLASH, 36 MHz, RISC MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, LQFP-48
文件頁(yè)數(shù): 51/72頁(yè)
文件大?。?/td> 996K
代理商: STM32F101C8T6
STM32F101xx
Electrical characteristics
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 7.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
SPI characteristics(1)
1.
TBD = to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
TBD
MHz
Slave mode
0
TBD
tr(SCK)
tf(SCK)
SPI clock rise and fall time
Capacitive load: C = 50 pF
TBD
ns
tsu(NSS)
(2)
2.
Values based on design simulation and/or characterization results, and not tested in production.
NSS setup time
Slave mode
0
th(NSS)
NSS hold time
Slave mode(3)
3.
Values based on device characterization, not tested in production.
0
tw(SCKL)
SCK high and low time
Master mode, fPCLK = TBD,
presc = TBD
TBD
tsu(MI)
tsu(SI)
Data input setup time
Master mode
TBD
Slave mode
TBD
th(MI)
th(SI)
Data input hold time
Master mode
TBD
Slave mode
TBD
Master mode, fPCLK = TBD
TBD(4)
4.
Depends on fPCLK. For example, if fPCLK= 8 MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns.
Slave mode, fPCLK = TBD
TBD(4)
ta(SO)
5.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time
Slave mode
TBD
Slave mode, fPCLK = TBD
TBD
tdis(SO)
6.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time
Slave mode
TBD
tv(SO)
Data output valid time
Slave mode (after enable edge)
TBD
fPCLK = TBD
TBD
Data output valid time
Master mode (after enable edge)
TBD
fPCLK = TBD
TBD
th(SO)
Data output hold time
Slave mode (after enable edge)
TBD
Master mode (after enable edge)
TBD
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