參數(shù)資料
型號(hào)： STK17T88-RF45
元件分類(lèi)： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： PROGRAMMABLE TIMER, PDSO48
封裝： 0.300 INCH, ROHS COMPLIANT, PLASTIC, SSOP-48
文件頁(yè)數(shù)： 15/29頁(yè)
文件大?。?/td> 535K
代理商： STK17T88-RF45
22
Jan, 2008
Document Control #ML0024 Rev 2.0
STK17T88
0x7FFA
Real Time Clock – Minutes
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Minutes
Minutes
Contains the BCD value of minutes. Lower nibble contains the lower digit and oper-
ates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to
5. The range for the register is 0-59.
0x7FF9
Real Time Clock – Seconds
D7
D6
D5
D4
D3
D2
D1
D0
0
10s Seconds
Seconds
Contains the BCD value of seconds. Lower nibble contains the lower digit and oper-
ates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The
range for the register is 0-59.
0x7FF8
Calibration
D7
D6
D5
D4
D3
D2
D1
D0
OSCEN
0
Calibrat
ion Sign
Calibration
OSCEN
Oscillator Enable. When set to 1, the oscillator is disabled. When set to 0, the oscillator
is enabled. Disabling the oscillator saves battery/capacitor power during storage.
Calibration
Sign
Determines if the calibration adjustment is applied as an addition to or as a subtraction
from the time-base.
Calibration
These five bits control the calibration of the clock.
0x7FF7
Watchdog Timer
D7
D6
D5
D4
D3
D2
D1
D0
WDS
WDW
WDT
WDS
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. The bit
is cleared automatically once the watchdog timer is reset. The WDS bit is write only.
Reading it always will return a 0.
WDW
Watchdog Write Enable. Set this bit to 1 to disable writing of the watchdog time-out
value (WDT5-WDT0). This allows the user to strobe the watchdog without disturbing
the time-out value. Setting this bit to 0 allows bits 5-0 to be written.
WDT
Watchdog time-out selection. The watchdog timer interval is selected by the 6-bit value
in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range or
time-out values is 31.25 ms (a setting of 1) to 2 seconds (setting of 3Fh). Setting the
watchdog timer register to 0 disables the timer. These bits can be written only if the
WDW bit was cleared to 0 on a previous cycle.
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