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參數(shù)資料
| 型號： | STE2001 |
| 英文描述： | Diac Thyristor; Leaded Process Compatible:Yes; Mounting Type:Through Hole; Package/Case:Axial Leaded; Breakover Voltage Min:27V; Breakover Voltage, Typ:32V RoHS Compliant: Yes |
| 中文描述： | 65 × 128單芯片LCD控制器/驅(qū)動 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 349K |
| 代理商： | STE2001 |
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STE2001
6/36
Notes: 1.
2. RES may be LOW or HIGH before V
DD1
goes HIGH.
3. If T
w(RES)
is longer than 500ns (typical) a reset may be generated.
4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V
IL
and V
IH
with
an input voltage swing of V
SS
to V
DD
5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification.
6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with T
SW
7. Cb is the capacitive load for each bus line.
8. T
H5
is the time from the previous SCLK positive edge to the negative edge of SCE
9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
10.C
VLCD
is the filtering capacitor on VLCDOUT
11.If T
w(RES)
is shorter than max. value a reset pulse is rejected.
T
fDA
Cb=100pF
25
ns
T
fDA
Cb=400pF
120
ns
C
b
Capacitive load for SDAH and
SCLH
100
400
pF
C
b
Capacitive load for SDAH + SDA
line and SCLH + SCL line
400
pF
T
SW
note 5
10
ns
PARALLEL INTERFACE
T
CY(EN)
Enable Cycle Time
V
DD
= 4.5V; Write
125
ns
T
W(EN)
Enable Pulse width
V
DD
= 4.5V; Write
60
ns
T
SU(A)
Address Set-up Time
V
DD
= 4.5V; Write
30
ns
T
H(A)
Address Hold Time
V
DD
= 4.5V; Write
50
ns
T
SU(D)
Data Set-Up Time
V
DD
= 4.5V; Write
30
ns
T
H(D)
Data Hold Time
V
DD
= 4.5V; Write
50
ns
SERIAL INTERFACE
F
SCLK
Clock Frequency
V
DD
= 4.5V
8
MHz
V
DD1
= 1.8V
5
MHz
T
CYC
Clock Cycle SCLK
V
DD
= 4.5V
125
ns
T
PWH1
SCLK pulse width HIGH
V
DD
= 4.5V
70
ns
T
PWL1
SCLK Pulse width LOW
V
DD
= 4.5V
70
ns
T
S2
SCE setup time
50
ns
T
H2
SCE hold time
50
ns
T
PWH2
SCE minimum high time
60
ns
T
H5
SCE start hold time
Note 8
60
ns
T
S3
SD/C setup time
60
ns
T
H3
SD/C hold time
40
ns
T
S4
SDIN setup time
40
ns
T
H4
SDIN hold time
40
ns
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
F
frame
f
---------
=
ELECTRICAL CHARACTERISTICS
(continued)
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