- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383840 > STA003 MPEG 2.5 LAYER III AUDIO DECODER PDF資料下載
參數(shù)資料
| 型號(hào)： | STA003 |
| 英文描述： | MPEG 2.5 LAYER III AUDIO DECODER |
| 中文描述： | 2.5第三層的MPEG音頻解碼器 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 299K |
| 代理商： | STA003 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁
5.5 DAC RELATED REGISTERS CONFIGURA-
TION
The different DAC registers must be configured
for 48kHz audio frequency: this is the reference
frequency. The STA003T will use these parame-
ters to derivate the register configurations for the
other audio frequencies (32, 24, 16, 12, 8 KHz)
according to the bistream informations.
The STA003T DAC and PLL register must be
configured according to the following steps:
1) OCLK_Freq determination from the DAC over-
sampling factor O_FAC.
As all STA003T registers must be configured
for 48KHz reference frequency, the OCLK
frquency is:
OCLK_Freq = O_FAC
48KHz
ex: O_FAC = 384, OCLK_Freq = 18.432MHz
2) PCMDIVIDER (0 x 54) register configuration.
The PCMDIVIDER register is used to config-
ure the frequency ratio between OCLK_Freq
and SCKT_Freq:
OCLK_Freq
(
2
(
1
+
PCMDIVIDER
))
The SCKT signal is the bit clock for the DAC
serial output. The SCKT frequency depends
on the number of bits to be transmitted to the
DAC during one LRCKT (Left/Right clock)
clock period. These number of bit depends on
the DAC precision (16, 18, 20 or 24bits) and
on the mode that is used to transmit the data
to the DAC (see figure 8). Once the
PCMCONF register is set according to the
DAC requirements, the number of SCKT clock
periods per LRCKT clock period is 16x2 or
32x2.
SCKT_Freq
=
a) LRCKT_period = 16x2 SCKT_periods
SCKT_Freq = LRCKT_Freq
32 =
OCLK_Freq
(
2
(
1
+
PCMDIVIDER
))
=
As the reference audio frequency is 48 KHz,
the previous relation becomes:
48KHz
32 = 48kHz
O_FAC (2
(1+ PCMDI-
VIDER))
Consequently:
PCMDIVIDER = (O_FAC/64)-1
ex: O_FAC = 384, PCMCONF[1:0] = 00,
PCMDIVIDER = 5
b) LRCKT_period = 32x2 SCKT_periods
SCKT_Freq = LRCKT_Freq
64 =
OCLK_Freq
(
2
(
1
+
PCMDIVIDER
))
=
Consequently:
PCMDIVIDER = (O_FAC/128)-1
3) Configuration of the PLL registers to set
OCLK_FREQ to the desired value computed
in step 1.
The PLL configuration in direct relation with
the XTI input clock frequency (14.72 MHz).
OCLK_freq
=
1
1
+
MFSDF
(
X
)
14.72MHz
1
+
PLLCTL_N
PLLCTL_M
+
1
+
PLLFRAC
65536
* MFSDF(X) is the value of the MFSDF(X)(0x61)
register.
* PLLCTL_N is the value of the PLLCTL_N
(0x07) register.
* PLLCTL_M is the value of the PLLCTL_N
(0x07) register.
* PLLFRAC (decimal) is the value of the
PLLFRAC_H and PLLFRAC_L registers as
PLLFRAC
=
256
PLLFRAC_L.
The following table gives the possible values for
these registers according to different OCLK_Freq
values. Other values can be supported on re-
quest to STMicroelectronics.
PLLFRAC_H
+
O_FAC
OCLK_Freq
at 48KHz
6.144MHz
12.288MHz
18.432MHz
PLLCTL_N
PLLCTL_M
PLLFRAC
MFSDF
128
256
384
0
0
0
12
12
11
23365
23365
34193
31
15
9
STA003T
30/32
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STA10 | ASIC |
| STA351A | General Purpose Sink Driver Array |
| STA352A | General Purpose Source Driver Array |
| STA474A | H-bridge Motor Driver Array |
| STB100NF03L-03T4 | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 100A I(D) | TO-263AB |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STA003T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MPEG 2.5 LAYER III AUDIO DECODER |
| STA011 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:L-band RF front-end for digital radio |
| STA011E | 制造商:ST 功能描述:DAB |
| STA013 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:MPEG 2.5 LAYER III AUDIO DECODER |
| STA013 | 功能描述:音頻 DSP MPEG Audio Decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。