參數(shù)資料
型號(hào)： ST95022M3TR
廠商： 意法半導(dǎo)體
元件分類： DRAM
英文描述： 2 Kbit Serial SPI EEPROM with High Speed Clock
中文描述： 2千位的SPI EEPROM，帶有高速時(shí)鐘
文件頁(yè)數(shù)： 6/16頁(yè)
文件大?。?/td> 113K
代理商： ST95022M3TR
Read Operation
The chip is first selected by putting S low. The serial
one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during
the rising edge of the clock (C). Then the data
stored in the memory at the selected address is
shifted out on the Q output pin; each bit being
shifted out during the falling edge of the clock (C).
The data stored in the memory at the next address
can be read in sequence by continuing to provide
clock pulses. The byte address is automatically
incremented to the next higher address after each
byte of data is shifted out. When the highest ad-
dress is reached, the address counter rolls over to
0h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by dese-
lecting the chip. The chip can be deselected at any
time during data output. Any read attempt during a
write cycle will be rejected and will deselect the
chip.
Byte Write Operation
Prior to any write attempt, the write enable latch
must be set by issuing the WREN instruction. First
the device is selected (S = low) and a serial WREN
instruction byte is issued. Then the product is de-
selected by taking S high. After the WREN instruc-
tion byte is sent, the ST95022 will set the write
enable latch and then remain in standby until it is
deselected. Then the write state is entered by
selecting the chip, issuing two bytes of instruction
and address, and one byte of data.
Chip Select (S) must remain low for the entire
duration of the operation. The product must be
deselected just after the eighth bit of data has been
latched in. If not, the write process is cancelled. As
soon as the product is deselected, the self-timed
write cycle is initiated. While the write is in progress,
the status register may be read to check BP1, BP0,
WEL and WIP. WIP is high during the self-timed
write cycle. When the cycle is completed, the write
enable latch is reset.
C
D
AI01558
S
Q
A7
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
A6 A5 A4 A3 A2 A1 A0
20 21 22 23
7
6
5
4
3
2
0
1
HIGH IMPEDANCE
DATA OUT
INSTRUCTION
BYTE ADDRESS
0
Figure 6. Read Operation Sequence
6/16
ST95022
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