參數(shù)資料
型號: ST90158M7
英文描述: 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
中文描述: 16位產(chǎn)品微控制器(MCU),并配備16至64K的光盤。檢察官辦公室或EPROM。 512 2K的內(nèi)存- ST9家庭
文件頁數(shù): 129/199頁
文件大?。?/td> 2813K
代理商: ST90158M7
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ST90158 - MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER
(Cont’d)
INTERRUPT/DMA CONTROL REGISTER
(IDCR)
R243 - Read/Write
Register Page: 9
Reset value: 1100 0111 (C7h)
Bit 7 =
CPE
:
Capture 0 EOB
.
This bit is set by hardware when the End Of Block
condition is reached during a Capture 0 DMA op-
eration with the Swap mode enabled. When Swap
mode is disabled (SWEN bit = “0”), the CPE bit is
forced to 1 by hardware.
0: No end of block condition
1: Capture 0 End of block
Bit 6 =
CME
:
Compare 0 EOB
.
This bit is set by hardware when the End Of Block
condition is reached during a Compare 0 DMA op-
eration with the Swap mode enabled. When the
Swap mode is disabled (SWEN bit = “0”), the CME
bit is forced to 1 by hardware.
0: No end of block condition
1: Compare 0 End of block
Bit 5 =
DCTS
:
DMA capture transfer source
.
This bit is set and cleared by software. It selects
the source of the DMA operation related to the
channel associated with the Capture 0.
Note:
The I/O port source is available only on spe-
cific devices.
0: REG0R register
1: I/O port.
Bit 4 =
DCTD
:
DMA compare transfer destination
.
This bit is set and cleared by software. It selects
the destination of the DMA operation related to the
channel associated with Compare 0.
Note:
The I/O port destination is available only on
specific devices.
0: CMP0R register
1: I/O port
Bit 3 =
SWEN
:
Swap function enable
.
This bit is set and cleared by software.
0: Disable Swap mode
1: Enable Swap mode for both DMA channels.
Bits 2:0 =
PL[2:0]:
Interrupt/DMA priority level
.
With these three bits it is possible to select the In-
terrupt and DMA priority level of each timer, as one
of eight levels (see Interrupt/DMA chapter).
I/O CONNECTION REGISTER (IOCR)
R248 - Read/Write
Register Page: 9
Reset value: 1111 1100 (FCh)
Bits
7:2 = not used.
Bit 1 =
SC1
:
Select connection odd.
This bit is set and cleared by software. It selects if
the TxOUTA and TxINA pins for Timer 1 and Timer
3 are connected on-chip or not.
0: T1OUTA / T1INA and T3OUTA/ T3INA uncon-
nected
1: T1OUTA connected internally to T1INA and
T3OUTA connected internally to T3INA
Bit 0 =
SC0
:
Select connection even.
This bit is set and cleared by software. It selects if
the TxOUTA and TxINA pins for Timer 0 and Timer
2 are connected on-chip or not.
0: T0OUTA / T0INA and T2OUTA/ T2INA uncon-
nected
1: T0OUTA connected internally to T0INA and
T2OUTA connected internally to T2INA
Note:
Timer 1 and 2 are available only on some
devices. Refer to the device block diagram and
register map.
7
0
CPE
CME DCTS
DCT
D
SWE
N
PL2
PL1
PL0
7
0
SC1
SC0
9
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