參數(shù)資料
型號(hào)： ST90158M7
英文描述： 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
中文描述： 16位產(chǎn)品微控制器（MCU），并配備16至64K的光盤(pán)。檢察官辦公室或EPROM。 512 2K的內(nèi)存- ST9家庭
文件頁(yè)數(shù)： 118/199頁(yè)
文件大?。?/td> 2813K
代理商： ST90158M7
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ST90158 - MULTIFUNCTION TIMER (MFT)
MULTIFUNCTION TIMER
(Cont’d)
Figure 63. Pointer Mapping for Register to
Register Transfers
9.3.5.4 DMA Transaction Priorities
Each Timer DMA transaction is a 16-bit operation,
therefore two bytes must be transferred sequen-
tially, by means of two DMA transfers. In order to
speed up each word transfer, the second byte
transfer is executed by automatically forcing the
peripheral priority to the highest level (000), re-
gardless of the previously set level. It is then re-
stored to its original value after executing the
transfer. Thus, once a request is being serviced,
its hardware priority is kept at the highest level re-
gardless of the other Timer internal sources, i.e.
once a Comp0 request is being serviced, it main-
tains a higher priority, even if a Capt0 request oc-
curs between the two byte transfers.
9.3.5.5 DMA Swap Mode
After a complete data table transfer, the transac-
tion counter is reset and an End Of Block (EOB)
condition occurs, the block transfer is completed.
The End Of Block Interrupt routine must at this
point reload both address and counter pointers of
the channel referred to by the End Of Block inter-
rupt source, if the application requires a continu-
ous high speed data flow. This procedure causes
speed limitations because of the time required for
the reload routine.
The SWAP feature overcomes this drawback, al-
lowing high speed continuous transfers. Bit 2 of
the DMA Counter Pointer Register (DCPR) and of
the DMA Address Pointer Register (DAPR), tog-
gles after every End Of Block condition, alternately
providing odd and even address (D2-D7) for the
pair of pointers, thus pointing to an updated pair,
after a block has been completely transferred. This
allows the User to update or read the first block
and to update the pointer values while the second
is being transferred. These two toggle bits are soft-
ware writable and readable, mapped in DCPR bit 2
for the CM0 channel, and in DAPR bit 2 for the
CP0 channel (though a DMA event on a channel,
in Swap mode, modifies a field in DAPR and
DCPR common to both channels, the DAPR/
DCPR content used in the transfer is always the bit
related to the correct channel).
SWAP mode can be enabled by the SWEN bit in
the IDCR Register.
WARNING
:
Enabling SWAP mode affects both
channels (CM0 and CP0).
Register File
8 bit Counter
XXXXXX11
Compare 0
8 bit Addr Pointer
XXXXXX10
8 bit Counter
XXXXXX01
Capture 0
8 bit Addr Pointer
XXXXXX00
9
相關(guān)PDF資料
PDF描述
ST90158M7LVT6 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
ST90158M7T6 8-BIT MICROCONTROLLER
ST90158M9 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
ST90158M9LVT6 8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
ST90158M9T6 8-BIT MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ST90158M7LVT6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
ST90158M7Q6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM
ST90158M7T6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
ST90158M9 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
ST90158M9LVT6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8/16-BIT MICROCONTROLLER (MCU) WITH 16 TO 64K ROM. OTP OR EPROM. 512 TO 2K RAM - ST9 + FAMILY
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