參數(shù)資料
型號： ST7LITE10F1M6
英文描述： FUSE PULLER/TESTERFUSE PULLER/TESTER; Depth, external:15mm; Length:60mm; Voltage rating, AC:24V; Voltage rating, DC:24V; Width, external:20mm
中文描述： ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時(shí)器。的SPI
文件頁數(shù)： 7/122頁
文件大?。?/td> 1716K
代理商： ST7LITE10F1M6
ST7LITE0, ST7SUPERLITE
7/122
PIN DESCRIPTION
(Cont’d)
Legend / Abbreviations for
Table 1
:
Type:
I = input, O = output, S = supply
In/Output level: C= CMOS 0.15V
DD
/0.85V
DD
with input trigger
C
T
= CMOS 0.3V
DD
/0.7V
DD
with input trigger
Output level:
HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input:
float = floating, wpu = weak pull-up, int = interrupt
1)
, ana = analog
– Output:
OD = open drain
2)
, PP = push-pull
Table 1. Device Pin Description
Note:
In the interrupt input column, “ei
x
” defines the associated external interrupt vector. If the weak pull-up col-
umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
Pin
n°
Pin Name
T
Level
Port / Control
Main
Function
(after reset)
Alternate Function
I
O
Input
Output
f
w
i
a
O
P
1
V
SS
S
Ground
2
V
DD
S
Main power supply
3
RESET
I/O
C
T
X
X
Top priority non maskable interrupt (active low)
ADC Analog Input 0 or SPI Slave
Select (active low)
4
PB0/AIN0/SS
I/O
C
T
X
ei3
X
X
Port B0
5
PB1/AIN1/SCK
I/O
C
T
X
X
X
X
Port B1
ADC Analog Input 1 or SPI Clock
6
PB2/AIN2/MISO
I/O
C
T
X
X
X
X
Port B2
ADC Analog Input 2 or SPI Master
In/ Slave Out Data
ADC Analog Input 3 or SPI Master
Out / Slave In Data
ADC Analog Input 4 or External
clock input
7
PB3/AIN3/MOSI
I/O
C
T
X
ei2
X
X
Port B3
8
PB4/AIN4/CLKIN
I/O
C
T
X
X
X
X
Port B4
9
PA7
I/O
C
T
X
ei1
X
X
Port A7
10
PA6 /MCO/ICCCLK
I/O
C
T
X
X
X
X
Port A6
Main Clock Output/In Circuit Com-
munication Clock.
Caution:
During reset, this pin
must be held at high level to avoid
entering ICC mode unexpectedly
(this is guaranteed by the internal
pull-up if the application leaves the
pin floating).
11
PA5/
ICCDATA
PA4
I/O C
T
HS
X
X
X
X
Port A5
In Circuit Communication Data
12
I/O C
T
HS
X
X
X
X
Port A4
13
PA3
I/O C
T
HS
X
X
X
X
Port A3
14
PA2/ATPWM0
I/O C
T
HS
X
X
X
X
Port A2
Auto-Reload Timer PWM0
15
PA1
I/O C
T
HS
X
X
X
X
Port A1
16
PA0/LTIC
I/O C
T
HS
X
ei0
X
X
Port A0
Lite Timer Input Capture
1
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