參數(shù)資料
型號: ST7LITE09Y0B6
英文描述: FUSE, FORK LIFT TRUCK, 200A; Current, fuse rating:200A; Voltage rating, DC:80V; Approval category:DIN 43560/1; Depth, external:20mm; Height:1mm; Length / Height, external:0.5mm; Width, external:82mm RoHS Compliant: Yes
中文描述: ST7LITE0。 ST7SUPERLITE - 8位微控制器單電壓閃存。數(shù)據(jù)EEPROM。 ADC的。定時器。的SPI
文件頁數(shù): 110/122頁
文件大?。?/td> 1716K
代理商: ST7LITE09Y0B6
ST7LITE0, ST7SUPERLITE
110/122
OPTION BYTES
(Cont’d)
OPTION BYTE 1
Bit 7 =
PLLx4x8
PLL Factor selection.
0: PLLx4
1: PLLx8
Bit 6 =
PLLOFF
PLL disable.
0: PLL enabled
1: PLL disabled (by-passed)
Bit 5 = Reserved, must always be 1.
Bit 4 =
OSC
RC
Oscillator selection
0: RC oscillator on
1: RC oscillator off
Table 20. List of valid option combinations
Note 1: see Clock Management Block diagram in
Figure 13
Bit 3:2 =
LVD[1:0]
Low voltage detection selection
These option bits enable the LVD block with a se-
lected threshold as shown in
Table 21
.
Table 21. LVD Threshold Configuration
Bit 1 =
WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Bit 0 =
WDG HALT
Watchdog Reset on Halt
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Operating conditions
Clock Source
Option Bits
PLLOFF
1
0
-
1
0
-
1
-
0
1
-
0
V
DD
range
PLL
off
x4
x8
off
x4
x8
off
x4
x8
off
x4
x8
Typ f
CPU
0.7MHz @3V
2.8MHz @3V
-
0-4MHz
4MHz
-
1MHz @5V
-
8MHz @5V
0-8MHz
-
8 MHz
OSC
0
0
-
1
1
-
0
-
0
1
-
1
PLLx4x8
x
0
-
x
0
-
x
-
1
x
-
1
2.4V - 3.3V
Internal RC 1%
External clock
3.3V - 5.5V
Internal RC 1%
External clock
Configuration
LVD1 LVD0
1
1
0
0
LVD Off
Highest Voltage Threshold (
4.1V)
Medium Voltage Threshold (
3.5V)
Lowest Voltage Threshold (
2.8V)
1
0
1
0
OPTION BYTE 0
7
0
OPTION BYTE 1
7
0
Reserved
SEC1 SEC0FR
FMP
W
PLL
x4x8
PLL
OFF
OSC LVD1 LVD0SW
WDG
HALT
Default
Value
1
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
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