參數(shù)資料
型號: ST78C36
廠商: Exar Corporation
英文描述: ECP/EPP Parallel Printer Port with 16 Byte FIFO(ECP/EPP并行打印機端口(帶16字節(jié)先進先出))
中文描述: 支持ECP / EPP并行打印機端口(支持ECP / EPP并行打印機端口(帶16字節(jié)先進先出),16字節(jié)FIFO)
文件頁數(shù): 12/27頁
文件大?。?/td> 204K
代理商: ST78C36
ST78C36/36A
6-32
Rev. 4.20
by a low driven on -SLCTIN for address 003 or
-AUTOFD (DATASTB*) for address 004 - 007 (read
and write cycles). When BUSY returns high for a
minimum of 60n second, IOCHRDY and the active
strobe will be driven high - allowing the host to
complete the I/O transaction.
To prevent a system stall, a 10 msecond TimeOut
aborts the cycle if it expires before BUSY returns high.
This TimeOut also sets bit 0 of DCR, which is cleared
by disabling EPP mode or writing a high to DCR bit 0.
TST MODE
This is ECR mode 110.
This mode allows data to be transferred (read or write
in any direction) between the FIFO and host at address
400 or DMA without activating the control interface (no
data is transferred to/from the peripheral). PDIR is
driven by DIR (can only be set in ECR mode 001);
-AUTOFD, INIT, and -SLCTIN are totem-pole.
Performing I/O cycles in this mode allows software to
test for the value of FIFOThreshold (FT) for both
output and input directions.
CFG MODE
This is ECR mode 111.
This mode enables I/O access to the configuration
registers CONF-A and CONF-B and disables I/O
access to the FIFO.
IRQ
The module has four sources of interrupt which may
be directed to -IRQ5, -IRQ7, -IRQ9 (see CONF-B) or
externally jumpered.
1) When DCR bit 4 (AIE) is high and -ACK is low the
interrupt is active.
2) When ECP mode is active, if ECR bit 4 is low when
ERROR transitions low or ECR bit 4 transitions low
when -Fault is low an interrupt pulse of at least 200n
seconds will be generated.
3) In FIFO modes (PPF, ECP, or TST) with ECR bit 3
(DMA) low, an interrupt pulse of at least 200n seconds
will be generated when ECR bit 2 (SI) is set low if there
are at least 8 empty bytes in the FIFO and PDIR = 0
or there are at least 8 filled bytes in the FIFO and PDIR
= 1. This interrupt will automatically disable itself by
setting ECR bit 2 high.
4) In FIFO modes (PPF, ECP, or TST) with (DMA
request enabled), an interrupt pulse of at least 200n
seconds will be generated when TC is received if PD-
ACK is low.
This interrupt will automatically disable itself and the
DMA request by setting ECR bit 2 high.
DMA
DMA cycles occur only between the host and the FIFO
data port (address 400) for PPF, ECP, or TST modes.
The selected DRQ(1, 2, or 3) will be driven high if ECR
bit 3 (DMA) is high and ECR bit 2 (SI) is low when
{PDIR = 0 and FIFO-F = 0} or {PDIR = 1 and FIFO-E
= 0} or TST mode is active.
When the selected D-ACK(1, 2, or 3) is low, -IOW will
transfer host data to the FIFO and -IOR will transfer
FIFO data to the host.
The selected DRQ will be driven low to terminate the
DMA channel when {PDIR = 0 and FIFO-F = 1} or
{PDIR = 1 and FIFO-E = 1} or ECR bit 2 (SI) goes high
(interrupt condition 4 above) or more than 32 consecu-
tive DMA data cycles (read or write) have occurred.
FIFO-F and FIFO-E terminated cycles will automati-
cally restart when their state returns low. Consecutive
cycle termination will automatically restart because
the counter is reset when the selected D-ACK goes
high. TC terminated cycles can only be restarted by
the host setting ECR bit 2 (SI) low again.
RLE
The module does not support RLE compression (indi-
cated by the “0” in CONF-B bit 7) but is required to
support RLE de-compression.
The host may send compressed data to the peripheral
by writing the RLE length byte (bit 7 = 0) to address 000
(NOTE: DMA cannot be used for this byte) which will
place a zero into the FIFO tag bit. This must be
followed immediately by the data byte being written to
the FIFO at address 400. These bytes will be trans-
ferred to the peripheral in the normal manner.
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