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參數(shù)資料
| 型號： | ST72521BR6 |
| 英文描述： | ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE |
| 中文描述： | ST72521B - 80/64-PIN 8位32至60,000 ROM的微處理器。 5個定時器。的SPI。脊髓損傷。 I2C總線。 CAN接口 |
| 文件頁數(shù)： | 41/198頁 |
| 文件大?。?/td> | 2504K |
| 代理商： | ST72521BR6 |
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ST72521B
41/198
POWER SAVING MODES
(Cont’d)
7.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).
7.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the ‘HALT’ in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see
Section
9.2 on page 55
for more details on the MCCSR
register).
The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see
Table 6, “Interrupt Mapping,” on
page 35
) or a RESET. When exiting ACTIVE-
HALT mode by means of an interrupt, no 256 or
4096 CPU cycle delay occurs. The CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see
Figure 25
).
When entering ACTIVE-HALT mode, the I[1:0] bits
in the CC register are forced to ‘10b’ to enable in-
terrupts. Therefore, if an interrupt is pending, the
MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note:
As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.
CAUTION:
When exiting ACTIVE-HALT mode fol-
lowing an interrupt, OIE bit of MCCSR register
must not be cleared before t
DELAY
after the inter-
rupt occurs (t
DELAY
= 256 or 4096 t
CPU
delay de-
pending on option byte). Otherwise, the ST7 en-
ters HALT mode for the remaining t
DELAY
period.
Figure 24. ACTIVE-HALT Timing Overview
Figure 25. ACTIVE-HALT Mode Flow-chart
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripheral clocked with an external clock source
can still be active.
3. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 6, “Interrupt Mapping,” on page 35
for more
details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and restored when the CC
register is popped.
MCCSR
OIE bit
Power Saving Mode entered when HALT
instruction is executed
0
1
HALT mode
ACTIVE-HALT mode
HALT
RUN
RUN
256 OR 4096 CPU
CYCLE DELAY
1)
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=1]
FETCH
VECTOR
ACTIVE
HALT
INSTRUCTION
(MCCSR.OIE=1)
RESET
INTERRUPT
3)
Y
N
N
Y
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
2)
ON
OFF
OFF
10
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
OFF
ON
XX
4)
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
ON
ON
XX
4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
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