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參數(shù)資料
| 型號(hào)： | ST70135 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | ASCOTTM DMT TRANSCEIVER |
| 中文描述： | ASCOTTM大唐收發(fā)器 |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 198K |
| 代理商： | ST70135 |
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ST70135A
11/29
This stream is still affected by carrier specific
channel distortion resulting in an attenuation of
the signal amplitude and a rotation of the signal
phase. To compensate, a Frequency domain
equalizer (FEQ) and a Rotor (phase shifter) are
implemented. The frequency domain equalization
performs an operation on the received vector in
order to match it with the associated point in the
constellation. The coefficient used to perform the
equalization are floating point, and may be
updated by hardware or software, using a
mechanism of active and inactive table to avoid
DMT synchro problems.In the transmit path, the
IFFT reverses the DMT symbol from frequency
domain to time domain.
The IFFT block is preceded by Fine Tune Gain
(FTG)
and
Rotor
stages,
compensation of the possible frequency mismatch
between the master clock frequency and the
transmitter clock frequency (which may be locked
to another reference).
The Inverse Fast Fourier Transform process is
used to transform from frequency domain to time
domain (transmit path). 256 positive frequencies
are processed, giving 512 samples in the time
domain.
The FFT module is a slave DSP engine controlled
by the firmware running on an external controller.
It works off line and communicates with other
blocks through buffers controlled by the ”Data
Symbol Timing Unit”. The DSP executes a
program stored in a RAM area, which constitutes
allowing
for
a
a flexible element that allows for future system
enhancements.
DPLL
The Digital PLL module receives a metric for the
phase error of the pilot tone. In general, the clock
frequencies at the ends (transmitter and receiver)
do not match exactly. The phase error is filtered
and integrated by a low pass filter, yielding an
estimation
of
the
frequency
processes can use this estimate to deal with the
frequency mismatch.
In particular, small accumulated phase error can
be compensated in the frequency domain by a
rotation of the received code constellation (Rotor).
Larger errors are compensated in the time domain
by inserting or deleting clock cycles in the sample
input sequence.
Eventually that leads to achieve less than 2ppm
between the two ends.
offset.
Various
Mapper/Demapper, Monitor, Trellis Coding,
FEQ Update
The Demapper converts the constellation points
computed by the FFT to a block of bits. This
means
to
identify
a
constellation plane. The Demapper supports
Trellis coded demodulation and provides a Viterbi
maximum likelihood estimator. When the Trellis is
active, the Demapper receives an indication for
the most likely constellation subset to be used.
point
in
a
2D
QAM
Figure 5 :
DMT Modem (Rx & Tx)
To/From
DSPFE
FFT
IFFT
FEQ
FTG
MAPPER
DEMAPPER
ROTOR
To/From
TC
TREILLIS
CODING
DECODING
MONITOR
FEQCOEFFICIENTS
FEQ
Update
Monitor
Indications
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST70135A | ASCOTTM DMT TRANSCEIVER |
| ST70136 | CPE ADSL ANALOG FRONT END |
| ST70136B | CPE ADSL ANALOG FRONT END |
| ST70136G | CPE ADSL ANALOG FRONT END |
| ST70137 | UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST70135A | 制造商:STMicroelectronics 功能描述:Modem Chip Single 144-Pin PQFP |
| ST70136 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136B | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136Q | 功能描述:射頻無線雜項(xiàng) ADSL Analg Front-End RoHS:否 制造商:Texas Instruments 工作頻率:112 kHz to 205 kHz 電源電壓-最大:3.6 V 電源電壓-最小:3 V 電源電流:8 mA 最大功率耗散: 工作溫度范圍:- 40 C to + 110 C 封裝 / 箱體:VQFN-48 封裝:Reel |
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