參數(shù)資料
型號: ST6389
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
中文描述: 8位微控制器對屏幕,電視調(diào)諧顯示器
文件頁數(shù): 44/82頁
文件大小: 718K
代理商: ST6389
44/82
ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
4.4 14-BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL
The ST638x on-chip voltage synthesis tuning pe-
ripheral has been integrated to allow the genera-
tion of tuning reference voltage in low/mid end TV
set applications. The peripheral is composed of a
14-bit counter that allows the conversion of the
digital content in a tuning voltage, available at the
VS output pin, by using Pulse Width Modification
(PWM), and Bit Rate Multiplier (BRM) techniques.
The 14-bit counter gives 16384 steps which allows
a resolution of approximately 2mV over a tuning
voltage of 32V; this corresponds to a tuning reso-
lution of about 40KHz per step in the UHF band
(the actual value will depend on the characteristics
of the tuner).
The tuning word consists of a 14-bit word con-
tained in the registers VSDATA1 (location 0EEh)
and VSDATA2 (location 0EFh). Coarse tuning
(PWM) is performed using the seven MSBits,
while fine tuning (BRM) is performed using the
data in the seven LSBits. With all zeros loaded the
output is zero; as the tuning voltage increases
from all zeros, the number of pulses in one period
increase to 128 with all pulses being the same
width. For values larger than 128, the PWM takes
over and the number of pulses in one period re-
mains constant at 128, but the width changes. At
the other end of the scale, when almost all ones
are loaded, the pulses will start to link together and
the number of pulses will decrease. When all ones
are loaded, the output will be almost 100% high
but will have a low pulse (1/16384 of the high
pulse).
4.4.1 Output Details
Inside the on-chip Voltage Synthesis are included
the register latches, a reference counter, PWM
and BRM control circuitry. In the ST638x the clock
for the 14-bit reference counter is 4MHz derived
from the 8MHz system clock. From the circuit point
of view, the seven most significant bits control the
coarse tuning, while the seven least significant bits
control the fine tuning. From the application and
software point of view, the 14 bits can be consid-
ered as one binary number.
As already mentioned the coarse tuning consists
of a PWM signal with 128 steps; we can consider
the fine tuning to cover 128 coarse tuning cycles.
The addition of pulses is described in the following
Table.
Table 14. . Fine Tuning Pulse Addition
The VS output pin has a standard drive push-pull
output configuration.
4.4.2 VS Tuning Cell Registers
Voltage Synthesis Data Register 1 (VSDR1)
Address: EEh - Write only
Reset Value: XXh
Caution
: This register contains at least one write
only bit. Single bit instructions (SET, RES, INC
and DEC) should not be used.
D7-D0
. These are the 8 least significant VS data
bits. Bit 0 is the LSB. This register is undefined on
reset.
Voltage Synthesis Data Register 2 (VSDR2)
Address: EFh - Write only
Reset Value: XXh
Caution
: This register contains at least one write
only bit. Single bit instructions (SET, RES, INC
and DEC) should not be used.
D7-D6
. These bits are not used.
D5-D0
. These are the 6 most significant VS data
bits. Bit 5 is the MSB. This register is undefined on
reset.
Fine Tuning
(7 LSB)
N° of pulses added at the
following cycles
(0... 127)
64
32, 96
16, 48, 80, 112
8, 24,....104, 120
4, 12,....116, 124
2, 6,.....122, 126
1, 3,.....125, 127
0000001
0000010
0000100
0001000
0010000
0100000
1000000
7
0
VSDR1
7
VSDR1
6
VSDR1
5
VSDR1
4
VSDR1
3
VSDR1
2
VSDR1
1
VSDR1
0
7
0
-
-
VSDR2
5
VSDR2
4
VSDR2
3
VSDR2
2
VSDR2
1
VSDR2
0
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