參數(shù)資料
型號: ST6389
廠商: 意法半導(dǎo)體
英文描述: 8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING
中文描述: 8位微控制器對屏幕,電視調(diào)諧顯示器
文件頁數(shù): 41/82頁
文件大小: 718K
代理商: ST6389
41/82
ST6380, ST6381, ST6382, ST6383, ST6388, ST6389
SERIAL PERIPHERAL INTERFACE
(Cont’d)
4.3.4 STD SPI Protocol (Shift Register)
This protocol is similar to the I
2
C BUS with the ex-
ception that there is no acknowledge pulse and
there are no stop or start bits. The clock cannot be
slowed down by the external peripherals.
In this case all three outputs should be high in or-
der not to lock the software I/Os from functioning.
SPI Standard Bus Protocol: The standard bus pro-
tocol is selected by loading the SPI Control Regis-
ter 1 (SCR1 Add. EBh). Bit 0 named I2C must be
set at one and bit 1 named STD must be reset.
When the standard bus protocol is selected bit 2 of
the SCR1 is meaningless.
This bit named STOP bit is used only in I
2
C BUS
or SBUS. However take care that THE STOP BIT
MUST BE RESET WHEN THE STANDARD PRO-
TOCOL IS USED. This bit is set to ZERO after RE-
SET.
Figure 29. Software Bus (Hardware Bus Disabled) Timing Diagram
4.3.5 SPI Data/Control Register
For I/O details on SCL (Serial Clock), SDA (Serial
Data) and SEN (Serial Enable) please refer to I/O
Ports description with reference to the following
registers:
Port C data register, Address C2h (Read/Write).
- BIT D0 “SCL”
- BIT D1 “SDA”
- BIT D3 “SEN”
Port C data direction register, Address C6h (Read/
Write).
SPI Serial Data Register (SSDR)
Address: CCh - Read/Write
Reset Value: XXh
SSDR7-0
. These are the SPI data bits. They can
be neither read nor written when SPI is operating
(BUSY bit set). They are undefined after reset.
VA00453
0
2
3
4
1
6
7
5
IDENT (was SEN, this is optionally controlled by software; output
as far as hardware is concerned is high).
CLOCK
(was SCL)
DATA
(was SDA, TRANSMIT)
DATA
(was SDA, RECEIVE)
7
0
SSDR
7
SSDR
6
SSDR
5
SSDR
4
SSDR
3
SSDR
2
SSDR
1
SSDR
0
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