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參數(shù)資料
| 型號(hào)： | ST62E85BG1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQFP80 |
| 封裝： | CERAMIC, QFP-80 |
| 文件頁數(shù)： | 40/78頁 |
| 文件大?。?/td> | 868K |
| 代理商： | ST62E85BG1 |
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Obsolete
Product(s)
- Obsolete
Product(s)
45/78
ST62T85B/E85B
AUTO-RELOAD TIMER (Cont’d)
4.3.3 AR Timer Registers
AR Mode Control Register (ARMC)
Address: E5h
—
Read/Write
Reset status: 00h
The AR Mode Control Register ARMC is used to
program the different operating modes of the AR
Timer, to enable the clock and to initialize the
counter. It can be read and written to by the Core
and it is cleared on system reset (the AR Timer is
disabled).
Bit 7 = TLCD:
Timer Load Bit. This bit, when set,
will cause the contents of ARRC register to be
loaded into the counter and the contents of the
prescaler register, ARPSC, are cleared in order to
initialize the timer before starting to count. This bit
is write-only and any attempt to read it will yield a
logical zero.
Bit 6 = TEN
: Timer Clock Enable. This bit, when
set, allows the timer to count. When cleared, it will
stop the timer and freeze ARPSC and ARTSC.
Bit 5-4. Reserved. Must be cleared to zero
Bit 3 = CPIE:
Compare Interrupt Enable. This bit,
when set, enables the compare interrupt request.
If CPIE is reset, the compare interrupt request is
masked. If CPIE is set and the related flag, CPF, in
the ARSC0 register is also set, an interrupt re-
quest is generated.
Bit 2 = OVIE:
Overflow Interrupt. This bit, when
set, enables the overflow interrupt request. If OVIE
is reset, the compare interrupt request is masked.
If OVIE is set and the related flag, OVF in the
ARSC0 register is also set, an interrupt request is
generated.
Bit 1-0. Reserved. Must be cleared to zero
AR Timer Status/Control Registers ARSC0 &
ARSC1. These registers contain the AR Timer sta-
tus information bits and also allow the program-
ming of clock sources, active edge and prescaler
multiplexer setting.
ARSC0 register bits 0,1 and 2 contain the interrupt
flags of the AR Timer. These bits are read normal-
ly. Each one may be reset by software. Writing a
one does not affect the bit value.
AR Status Control Register 0 (ARSC0)
Address: E6h
—
Read/Clear
Bits 7-2 = D7-D2:
Unused
Bit 1 = CPF:
Compare Interrupt Flag. This bit is set
if the contents of the counter and the ARCP regis-
ter are equal. The flag is cleared by writing a zero
to the CPF bit.
Bit 0 = OVF:
Overflow Interrupt Flag. This bit is set
by a transition of the counter from FFh to 00h
(overflow). The flag is cleared by writing a zero to
the OVF bit.
70
TCLD
TEN
-
CPIE
OVIE
-
70
D7
D6
D5
D4
D3
D2
CPF
OVF
45
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