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參數(shù)資料
| 型號： | ST62E35BG1 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 56/84頁 |
| 文件大?。?/td> | 918K |
| 代理商： | ST62E35BG1 |
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ST62T53C/T60C/T63C ST62E60C
SERIAL PERIPHERAL INTERFACE SPI
(Cont’d)
SPI DIV Register (DIV)
Address: E1h
—
Read/Write
Reset status: 00h
The SPIDIV register defines the transmission rate
and frame format and contains the interrupt flag.
Bits CD0-CD2, DIV3-DIV6 are read/write while
SPINT can be read and cleared only. Write access
is not allowed if SPRUN in the MOD register is set.
Bit 7 =
SPINT
:
Interrupt Flag.
If SPIE bit=1, SPINT
is automatically set to one by the SPI at the end of
a transmission or reception and an interrupt re-
quest can be generated depending on the state of
the interrupt mask bit in the MOD control register.
This bit is write and read and must be cleared by
user software at the end of the interrupt service
routine.
Bit 6-3 =
DIV6-DIV3
:
Burst Mode Bit Clock Period
Selection.
Define the number of shift register bits
that are transmitted or received in a frame. The
available selections are listed in
Table 16
. The
normal maximum setting is 8 bits, since the shift
register is 8 bits wide. Note that by setting a great-
er number of bits, in conjunction with the SPIN bit
in the MOD register, unwanted data bits may be fil-
tered from the data stream.
Bit 2-0 =
CD2-CD0
:
Base/Bit Clock Rate Selec-
tion
. Define the division ratio between the core
clock (f
INT
divided by 13) and the clock supplied to
the Shift Register in Master mode.
Table 15. Base/Bit Clock Ratio Selection
Note
: For example, when an 8MHz CPU clock is
used, asynchronous operation at 9600 Baud is
possible (8MHz/13/64). Other Baud rates are
available by proportionally selecting division fac-
tors depending on CPU clock frequency.
Data setup time on Sin is typically 250ns min, while
data hold time is typically 50ns min.
SPI Data/Shift Register (SPIDSR)
Address: E0h
—
Reset status: XXh
Read/Write
SPIDSR is read/write, however write access is not
allowed if the SPRUN bit of Mode Control register
is set to one.
Data is sampled into SPDSR on the SCK edge de-
termined by the CPOL and CPHA bits. The affect
of these setting is shown in the following diagrams.
The Shift Register transmits and receives the Most
Significant Bit first.
Bit 7-0 =
DSR7-DSR0
:
Data Bits.
These are the
SPI shift register data bits.
Miscellaneous Register (MISCR)
Address: DDh
—
Write only
Reset status: xxxxxxxb
Bit 7-1 =
D7-D1
:
Reserved.
Bit 0 =
D0
:
Bit 0.
This bit, when set, selects the
Sout pin as the SPI output line. When this bit is
cleared, Sout acts as a standard I/O line.
7
0
SPINT
DOV6
DIV5
DIV4
DIV3
CD2
CD1
CD0
CD2-CD0
0
0
1
1
0
0
1
1
Divide Ratio (decimal)
Divide by 1
Divide by 2
Divide by 4
Divide by 8
Divide by 16
Divide by 32
Divide by 64
Divide by 256
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
DIV6-DIV3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Number of bits sent
Reserved (not to be used)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Refer to the
description of the
DIV6-DIV3 bits in
the DIV Register
7
0
D7
D6
D5
D4
D3
D2
D1
D0
7
0
-
-
-
-
-
-
-
D0
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