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參數(shù)資料
| 型號： | ST62E35BG1 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 21/84頁 |
| 文件大?。?/td> | 918K |
| 代理商： | ST62E35BG1 |
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21/84
ST62T53C/T60C/T63C ST62E60C
CLOCK SYSTEM
(Cont’d)
Oscillator Control Registers
Address: DCh
Reset State: 00h
—
Write only
Bit 7-4. These bits are not used.
Bit 3. Reserved. Cleared at Reset. Must be kept
cleared.
Bit 2. Reserved. Must be kept low.
RS1-RS0. These bits select the division ratio of
the Oscillator Divider in order to generate the inter-
nal frequency. The following selctions are availa-
ble:
Note
: Care is required when handling the OSCR
register as some bits are write only. For this rea-
son, it is not allowed to change the OSCR contents
while executing interrupt service routine, as the
service routine cannot save and then restore its
previous content. If it is impossible to avoid the
writing of this register in interrupt service routine,
an image of this register must be saved in a RAM
location, and each time the program writes to
OSCR it must write also to the image register. The
image register must be written first, so if an inter-
rupt occurs between the two instructions the
OSCR is not affected.
7
0
-
-
-
-
OSCR
3
-
RS1
RS0
RS1
0
0
1
1
RS0
0
1
0
1
Division Ratio
1
2
4
4
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