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參數(shù)資料
| 型號： | ST52513Y2 |
| 英文描述： | MAX 3000A CPLD 256 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 84/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513Y2 |
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12 SERIAL COMMUNICATION INTERFACE
The
Serial
Communication
Interface
(SCI)
integrated into ST52F501L/F502L provides a
general purpose shift register peripheral, several
widely distributed devices to be linked, through
their SCI subsystem. SCI gives a serial interface
providing communication with the speed from less
than 300 up to over 115200 baud, and a flexible
character format.
SCI is a full-duplex UART-type asynchronous
system with standard Non Return to Zero (NRZ)
format for the transmitted/received bit. The length
of the transmitted word is 10/11 bits (1 start bit, 8/
9 data bits, 1 stop bit).
SCI is composed of three modules: Receiver,
Transmitter and Baud-Rate Generator.
12.1 SCI Receiver block
The
SCI
Receiver
block
manages
the
synchronization of the serial data stream and
stores the data characters. The SCI Receiver is
mainly composed of two sub-systems: Recovery
Buffer Block and SCDR_RX Block.
SCI receives data deriving from the RX pin and
drives the Recovery Buffer Block, which is a high-
speed shift register operating at a clock frequency
(CLOCK_RX) 16 times higher than the fixed baud
rate (CLOCK_TX). This sampling rate, higher than
the Baud Rate clock, detects the START condition,
Noise error and Frame error.
When the SCI Receiver is in IDLE status, it is
waiting for the START condition, which is obtained
with a logic level of 0, consecutive to a logic level
1. This condition is detected if, with the fixed
sampling time, a logic level 0 is sampled after three
logic levels of 1.
The recognition of the START bit forces the SCI
Receiver
Block
to
start
a
data
acquisition
sequence.
The data acquisition sequence is configured by the
apposite Configuration Register, allowing the
following data frame formats (see Figure 12.1):
Figure 12.1 SCI transmitted word structures
s
8 bit length, 1 stop bit, no parity bit
s
8 bit length, 2 stop bit, no parity bit
s
8 bit length, 1 stop bit, with parity bit
s
9 bit length, 1 stop bit, no parity bit
The parity bit (if used) can be configured for even
or odd parity check. If the 9-bit length format is
configured, this bit is used in transmission for the
ninth bit (see below). The ninth bit received can be
read in the R8 bit of the SCI Status Register,
address 37 (035h) bit 2 (see Figure 12.3).
Figure 12.2 SCI Block Diagram
7
6
5
43
2
10
8
9
7
6
5
43
2
1
0
8
9
10
STOP
DATA
START
STOP
DATA
START
SCI
Register File
SCDR_TX
LDPR/LDPE/LDPI
Baud-Rate
Generator
LDRI
SHIFT REGISTER
SCDR_RX
RECOVERY BUFFER
RX
TX
SCI Transmitter
SCI Receiver
MCLK
Program/Data
Memory
IR
OR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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