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參數(shù)資料
| 型號： | ST52513Y2 |
| 英文描述： | MAX 3000A CPLD 256 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 57/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513Y2 |
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8 I/O PORTS
8.1 Introduction
ST52F501L/F502L are characterized by flexible
individually
programmable
multi-functional
I/O
lines. The ST52F501L/F502L supplies devices
with up to 3 Ports (named from A to C) with up to
24 I/O lines.
Each pin can be used as a digital I/O or can be
connected with a peripheral (Alternate Function).
The I/O lines belonging to Port A and Port B can
also be used to generate Port Interrupts.
The I/O Port pins can be configured in the following
modes:
s
Input high impedance (reset state)
s
Input with pull-up
s
Output with pull-up
s
Output push-pull
s
Output with weak pull-up
s
Output open drain
s
Interrupt with pull-up
s
Interrupt without pull-up
These
eight
modes
can
be
selected
by
programming three Configuration Registers for
each Port. All the pins that belong to the same Port
can be configured separately by setting the
corresponding bits in the three registers (see
Register Description).
To avoid side effects, the Configuration Registers
register are latched only when the Direction
Register (PORT_x_DDR) is written. For this
reason this register must be always written when
modifying the pin configuration.
All the I/O digital pins are TTL compatible and have
a Schmitt Trigger. The output buffer can supply
high current sink (up to 8mA).
Figure 8.1 Digital Pin
8.2 Input Mode
The pins configured as input can be read by
accessing the corresponding Port Input Register
by means of the LDRI instruction. The addresses
for Port A, B and C are respectively 0 (00h), 1
(01h), and 2 (02h).
When executing the LDRI instruction all the signals
connected to the input pins of the Port are read and
the logical value is copied in the specified Register
File location. If some pins are configured in output,
the port buffer contents, which are the last written
logical values in the output pins, are read.
8.3 Output Mode
The pins configured as output can be written by
accessing the corresponding Port Output Register
by means of the LDPR, LDPI and LDPE
instructions. The addresses for Port A, B and C are
respectively, 0 (00h), 1 (01h), and 2 (02h).
When executing the above mentioned instructions,
the Port buffer is written and the Port pin signals
are modified. If some pins are configured as input
or as interrupt, the values are ignored.
8.4 Interrupt Mode
The pins configured as Interrupt Mode can
generate a Port Interrupt request. One Interrupt
vector is associated to Port A and one to Port B
and C. More pins of the ports can act as source at
the same time. The Configuration Registers switch
the signals deriving from interrupt pins to an OR
gate that generates the interrupt request signal.
The signal deriving from the pins can be read,
allowing the discrimination of the interrupt sources
when more than one pin can generate the interrupt
signal.
The interrupt trigger can be configured either in the
rising or falling edge of the external signal.
PAD
PU LL U P
EN A BL E
D IGITAL OUT
EN A BL E
DAT A
OU T
PO R T A,C ,D,E
PIN
DAT A
IN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514G3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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