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| 型號： | ST52501LG1 |
| 英文描述： | MAX 7000 CPLD 128 MC 160-PQFP |
| 中文描述： | 8位紅外驅(qū)動重癥監(jiān)護病房。定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。低電壓 |
| 文件頁數(shù)： | 5/106頁 |
| 文件大小： | 1355K |
| 代理商： | ST52501LG1 |
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14.5 SPI Register Description
In the following sections describe the registers
used by the SPI. In the 16 pin devices the SPI is
not present and the described register aren’t used
14.5.1 SPI Configuration Registers.
SPI Control Register (SPI_CR)
Configuration Register 20 (014h) Read/Write
Reset Value: 0000 0000 (00h)
Bit 7: SPIE Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever
SPIF=1 or MODF=1 in SPI_STATUS_CR
Bit 6: SPE Serial peripheral output enable.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 14.4.5 Master
0: I/O port connected to pins
1: SPI alternate functions connected to pins
Note: The SPE bit is cleared by reset, so the SPI
peripheral is not initially connected to the pins.
Bit 5: SPR2 Divider Enable.
This bit is set and cleared by software and it
is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4: MSTR Master/Slave mode select.
This bit is set and cleared by software. It is
also cleared by hardware when, in master
mode, SS=0 (see Section 14.4.5 Master
0: Slave mode is selected
1: Master mode is selected, the function of
the SCK pin changes from an input to an
output and the functions of the MISO and
MOSI pins are reversed.
Bit 3: CPOL Clock polarity.
This bit is set and cleared by software. This
bit determines the steady state of the serial
Clock. The CPOL bit affects both the master
and slave modes.
0: The steady state is a low value at the SCK
pin.
1: The steady state is a high value at the SCK
pin.
Note: SPI must be disabled by resetting the SPE
bit if CPOL is changed at the communication byte
boundaries.
Bit 2: CPHA Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data
capture edge.
1: The second clock transition is the first
capture edge.
Bit 1-0: SPR1-SPR0 Serial peripheral rate.
These bits are set and cleared by software.
Used with the SPR2 bit, they select one of six
baud rates to be used as the serial clock
when the device is a master (see Table 14.1).
These 2 bits have no effect in slave mode.
Remark: It is recommended to write the SPI_CR
register after the SPI_STATUS_CR register when
working in master mode, vice versa when working
in slave mode.
SPI Control-Status Register (SPI_STATUS_CR)
Configuration Register 21 (015h) Read/Write
Reset Value: 0000 0000 (00h)
70
SPIE
SPE
SPR2
MSTR
CPOL
CPHA
SPR1
SPR2
Table 14.1 Serial Peripheral Baud Rate
Serial Clock
SPR2
SPR1
SPR0
fCKM/2
100
fCKM/4
000
fCKM/8
001
fCKM/16
110
fCKM/32
010
fCKM/64
011
70
SPIF
WCOL
OR
MODF
-
SOD
SSM
SSI
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| ST52501LG3 | MAX 7000 CPLD 128 MC 100-TQFP |
| ST52501LK1 | MAX 7000 CPLD 160 MC 84-PLCC |
| ST52501LK2 | MAX 7000 CPLD 160 MC 100-TQFP |
| ST52501LK3 | MAX 7000 CPLD 192 MC 160-PQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52501LG2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LG3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LK1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LK2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LK3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
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