參數(shù)資料
型號: ST52440F3
英文描述: MAX 7000 CPLD 64 MC 44-TQFP
中文描述: 8位重癥監(jiān)護病房與定時器/脈寬調(diào)制。模擬比較器。可控硅/ PWM定時器。水分散粒劑。提供了8K存儲器
文件頁數(shù): 11/88頁
文件大?。?/td> 1162K
代理商: ST52440F3
ST52T430/E430
19/88
2.3.4 Output Registers.
The Output Registers (OR) consist of 10 registers
containing data for the microcontroller peripherals
including the I/O Ports.
All registers can be specified by using a decimal
address (for example, 1 identifies the second OR).
By using LOAD instructions the Output Registers
(OR) may be set by using values stored in the
Program Memory (LDPE) or in RAM (LDPR)
The assembler instruction:
LDPR OR_i RAM_Reg.
loads the value of the RAM location identified by
the address RAM_Reg in the OR i-th Table 2.4
describes OR.
In order to simplify the concept, a mnemonic name
is assigned to OR. The same names are used in
FUZZYSTUDIOTM 4.0 development tools.
Use and meaning of each register will be described
in further details in the corresponding section.
REG_CONF 4
PORT A
Set the relative bit like digital input
or digital output
REG_CONF 5
PWM/TIMER 0
PWM/Timer 0 Working mode
Configuration
REG_CONF 6
PWM/TIMER 0
PWM/TIMER 0 Prescaler
configuration and output waveform
selection.
REG_CONF 7
PWM/TIMER 0
PWM/TIMER 0 Working Mode
Configuration
REG_CONF 8
PWM/TIMER 1
PWM/TIMER 1 Working Mode
Configuration
REG_CONF 9
PWM/TIMER 1
PWM/TIMER 1 Prescaler
configuration and output waveform
selection.
REG_CONF 10
PWM/TIMER 2
PWM/TIMER 2 Working Mode
Configuration
REG_CONF 11
PWM/TIMER 2
PWM/Timer 2 Prescaler
configuration and output waveform
selection.
REG_CONF 12
PORT A
Set the bit 0,1 and 2 like Digital I/O
or complementary Timers Output.
REG_CONF 13
PORT B
Set the relative bit like digital input
or digital output.
REG_CONF 14
PORT B
Set the relative I/O like Digital or
Analog.
REG_CONF 15
PORT C
Set the relative I/O like digital input
or digital output
REG_CONF 16
PORT C
Set the relative I/O like Digital I/O
or Timers Output
REG_CONF 17
Interrupt Priority
Set the Interrupts priority
REG_CONF 18
Interrupt Priority
Set the Interrupts priority
REG_CONF 19
SCI
Set the SCI working mode
REG_CONF 20
SCI
Set the SCI working mode
Table 2.3 Configuration Registers (continued)
CONFIGURATION REGISTER
PERIPHERAL
DESCRIPTION
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