參數(shù)資料
型號(hào): ST2202
廠商: Electronic Theatre Controls, Inc.
英文描述: 8 BIT Integrated Microcontroller with 256K Bytes ROM
中文描述: 8位微控制器集成256K字節(jié)ROM的
文件頁數(shù): 55/65頁
文件大?。?/td> 1946K
代理商: ST2202
Sitronix
ST2202
Ver 2.0a
55/65
2003-May-05
1
1
9
9
.
.
D
D
I
I
R
R
E
E
C
C
T
T
M
M
E
E
M
M
O
O
R
R
Y
Y
A
A
C
C
C
C
E
E
S
S
S
S
(
(
D
D
M
M
A
A
)
)
To speed up the memory access of this system, a
sequential direct memory access (DMA) controller is
designed-in. DMA can perform memory transfer function
more efficient than CPU does. While DMA working, data
ROM register (DRR) will disable and DMA use DMA
memory bank register (DMR) to access ROM. After DMA
complete, ROM bank control still return to DRR.
With the help of DMR can make DMS across bank
boundary smoothly, but DMR is only valid for DMS.
The
DMR can automatic increases when DMS across bank
boundary.
Note: Location of source data can not fall in the range
of internal SRAM( that is the range of
0100H~FFFH).
LCD
DMA
CPU
SRAM
ROM
LCD_CTL
FIGURE 19-1 System Block Diagram
19.1 DMA Control Register
The control register is shown as following:
TABLE 19-2 DMA Control Register (LCTL)
Bit 6
Bit 5
Bit 4
DMS[6]
DMS[5]
DMS[4]
DMS[15] DMS[14] DMS[13] DMS[12] DMS[11] DMS[10] DMS[9] DMS[8]
DMD[7]
DMD[6]
DMD[5]
DMD[4]
DMD[3]
DMD[15] DMD[14] DMD[13] DMD[12] DMD[11] DMD[10] DMD[9] DMD[8]
DCNT[7] DCNT[6] DCNT[5] DCNT[4] DCNT[3] DCNT[2] DCNT[1] DCNT[0]
-
-
-
DMAM DCNT[11] DCNT[10] DCNT[9] DCNT[8] - - -
DMR[7]
DMR[6]
DMR[5]
DMR[4]
DMR[3]
-
-
-
-
-
Address Name R/W
$028
DMSL
$029
DMSH
$02A
DMDL
$02B DMDH
$02C DCNTL
$02D DCNTH
$036
DMRL
$037
DMRH
DMS[15:0] :
DMA source data starting address register
DMD[15:0]:
DMA destination data starting address register
DCNT[11:0]:
DMA moving data byte counter register
DMR[10:0]:
DMA source data bank register (
DMR
works only when
DMS
is in the range from 8000h to FFFFh).
DMAM
(
DCNTH[4]
)
:
DMA destination address increasing mode selection bit
0 = Destination address increases automatically.
1 = Destination address is fixed.
Bit 7
DMS[7]
Bit 3
DMS[3]
Bit 2
DMS[2]
Bit 1
DMS[1] DMS[0]
Bit 0
Default
W
W
W
W
W
W
R/W
R/W
DMD[2]
DMD[1] DMD[0]
DMR[2]
DMR[10] DMR[9] DMR[8] - - - - -000
DMR[1] DMR[0] 0000 0000
The DMA always move (DCNT+1) bytes of data. DMA will
start right after CPU write data into register DCNTL. During
the DMA operation, the CPU hold, until the DMA transfer
completed. The DMR register reset to “$00” on real chip,
but Emulation Board is “unknown”, so recommend initial
DMR register before use.
Before Read/Write you have to
initial the PRR, DRR, DMR register when system reset.
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