
Sitronix
ST2202
Ver 2.0a
14/65
2003-May-05
9
9
.
.
G
G
P
P
I
I
O
O
The ST2202 consists of 48 general-purpose I/O (GPIO) which
are divided into six I/O ports: Port-A/B/C/D/E and Port-L.
Control registers of GPIO are shown as following and in TABLE
9-1.
Port data registers:
PA
~
PE, PL
Port direction control registers:
PCA
~
PCE, PCL
Port type select registers:
PSC
Port function select registers:
PFC
and
PFD
Port miscellaneous control register:
PMCR
TABLE 9-1 Summary Of Control Registers Of GPIO
Bit 6
Bit 5
Bit 4
PA[6]
PA[5]
PA[4]
PB[6]
PB[5]
PB[4]
PC[6]
PC[5]
PC[4]
PD[6]
PD[5]
PD[4]
PE[6]
PE[5]
PE[4]
PL[6]
PL[5]
PL[4]
PSC[7]
PSC[6]
PSC[5]
PSC[4]
PCA[7]
PCA[6]
PCA[5]
PCA[4]
PCB[7]
PCB[6]
PCB[5]
PCB[4]
PCC[7]
PCC[6]
PCC[5]
PCC[4]
PCD[7]
PCD[6]
PCD[5]
PCD[4]
PCE[7]
PCE[6]
PCE[5]
PCE[4]
PCL[7]
PCL[6]
PCL[5]
PCL[4]
RXD0
TXD0
SRDY
RXD1
TXD1
CS6
PULL
PDBN
INTEG
CSM1
Address Name
$000
$001
$002
$003
$004
$04C
$005
$008
$009
$00A
$00B
$00C
$04E
$00D
$00E
$00F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
R/W
R/W
Bit 7
PA[7]
PB[7]
PC[7]
PD[7]
PE[7]
PL[7]
Bit 3
PA[3]
PB[3]
PC[3]
PD[3]
PE[3]
PL[3]
PSC[3]
PCA[3]
PCB[3]
PCC[3]
PCD[3]
PCE[3]
PCL[3]
MOSI
CS4
CSM0
Bit 2
PA[2]
PB[2]
PC[2]
PD[2]
PE[2]
PL[2]
PSC[2]
PCA[2]
PCB[2]
PCC[2]
PCD[2]
PCE[2]
PCL[2]
MISO
CS3
BCO
Bit 1
PA[1]
PB[1]
PC[1]
PD[1]
PE[1]
PL[1]
PSC[1]
PCA[1]
PCB[1]
PCC[1]
PCD[1]
PCE[1]
PCL[1]
SCK
CS2
TCO1
Bit 0
PA[0]
PB[0]
PC[0]
PD[0]
PE[0]
PL[0]
PSC[0]
PCA[0]
PCB[0]
PCC[0]
PCD[0]
PCE[0]
PCL[0]
INTX
CS1
TCO0
Default
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1000 0000
PA
PB
PC
PD
PE
PL
PSC
PCA
PCB
PCC
PCD
PCE
PCL
PFC
PFD
PMCR
SS
CS5
Each single pin can be programmed to be input or output. This
is controlled by port direction control registers
PCx
. Setting bit
of
PCx
makes respective pin to output, and clearing this bit for
input. There are two options: pull-up/down for inputs of Port-C
but only pull-up for inputs of the other ports. In case of output,
there are open-drain/CMOS options for outputs of PortC but
only CMOS for the other ports. Refer to TABLE 9-2.
TABLE 9-2 I/O Types Of GPIO Ports
I/O Types
I/O Mode
Port-A/B/D/E/L
Pull-up/Pure
CMOS
Port-C
Input
Output
Pull-up/Pull-down/Pure
Open-drain/CMOS
In case of input function, port data registers
Px
reflect the
values on associated pins. Besides read instruction for data of
signals input, writing to register
Px
selects I/O types of pins,
pull-up or pull-down. Setting bits of all port data register
Px
to
select pull-up type. Clearing bits of only
PC
to select pull-down
type for pins of Port-C. There are no pull-down resistors for
Port-A/B/D/E and Port-L, thereby no pull-down resistors will be
enabled if clearing bits of
PA
,
PB
,
PD
,
PE
and
PL
. Pull-up
resistors of Port-A/B/D/E/L are also controlled by PULL bit (bit7
of port miscellaneous register
PMCR
), “0” is to disable, while
“1” is to enable them. The pull-up/pull-down resistors of Port-C
are further controlled by bits of port type select registers
PSC
.
They work in the same way with PULL bit of
PMCR
but only on
single pin, “0” is to disable, while “1” is to enable. Refer to
FIGURE 9-1.
Input Mode
VCC
PORT
DATA
REGISTER
( PDR )
PULL-UP
PMOS
PULL-UP
RD_INPUT
DATA INPUT
PORT
CONTROL
REGISTER
( PCR )
FIGURE 9-1 Configuration Of Inputs
In case of output function, Write to port data registers
Px
makes pins to output desired value. This value can also be
read back by read instruction. Besides Port-C, the output pins
are CMOS type. Port-C have two options of output types:
open-drain and CMOS, and is controlled by port type select
registers
PSC
. Clearing bits of registers
PSC
is for that disable
PMOS of output stage and left only NMOS, while setting bits is
for CMOS. Refer to FIGURE 9-2.
FIGURE 9-2 Configuration Of Outputs
Output Mode