參數(shù)資料
型號: ST20-SWC-PC
英文描述: Stratix II GX FPGA 130K FPGA-40
中文描述: 的ST20軟件開發(fā)和調(diào)試工具
文件頁數(shù): 4/21頁
文件大?。?/td> 360K
代理商: ST20-SWC-PC
ST20–SWC
4/21
2
The ST20 ANSI C Toolset provides a complete C cross-development system for the ST20. It can be
used to build single task and multi-tasking programs for the ST20. Programs developed with the
toolset are both source and binary compatible across all host development machines.
The ST20 ANSI C Toolset is available for the following development platforms:
IBM 386/486 PC and compatibles under MSDOS 5 and Windows 3.1, or later versions.
Code building tools
Sun 4 under SunOS 4.1.3 or Solaris 2.4 with X11 Release 4 server or OpenWindows 3, or
later versions.
2.1
How programs are built
The toolset build process is shown diagrammatically in Figure 1.
Figure 1
The tool chain
ANSI C source files may be separately compiled into object files The compiler and libraries are
described in section 2.2. The librarian may be used to collate object files into libraries. The linkerlinks
object files and libraries into fully resolved linked units.
A configuration descriptionis a text file describing the target hardware and how the software maps
onto it. The configurer converts the configuration description file into a configuration binaryfile. The
collector removes any debugging information, and uses the configuration binary to collect the linked
files with bootstrap code to make an executable file called a bootable file
During development and for hosted systems, the bootable file may be loaded down a hardware serial
link onto the target hardware using the application loader For stand-alone systems, the bootable file
may be converted, using the EPROM tool, to an industry standard EPROM format for programming
EPROMs.
In addition to loading programs down a hardware serial link, the application loader program provides
access to host operating system facilities through a remote procedure call mechanism. This method
is used to support the full ANSI C run-time library.
A memory configurer tool is supplied for describing a ST20450 memory configuration. This data is
used to initialize the memory interface of the ST20450. The memory interface can be initialized either
using the hardware serial link or from ROM.
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