參數(shù)資料
型號(hào)： ST16C654
廠商： Exar Corporation
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Linear Voltage Regulator IC; Output Current Max:350mA; Supply Voltage Max:6V; Package/Case:8-TSSOP; Output Current:600mA; Output Voltage:5V; Current Rating:30.05A; Leaded Process Compatible:No; Output Voltage Max:5V
中文描述： 2.97V至5.5V四路UART的64字節(jié)FIFO
文件頁(yè)數(shù)： 31/51頁(yè)
文件大?。?/td> 968K
代理商： ST16C654
ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
31
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be set to a logic zero during 68 mode.
Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During loopback mode, it sets
OP2# internally to a logic 1.
Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During loopback mode, it sets OP2# internally
to a logic 0.
T
ABLE
14: INT O
UTPUT
M
ODES
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the 654 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR
bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an
error is in the RHR.
LSR[0]: Receive Data Ready Indicator
Logic 0 = No data in receive holding register or FIFO (default).
Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
INTSEL
P
IN
MCR
B
IT
-3
INT A-D O
UTPUTS
IN
16 M
ODE
0
0
Three-State
0
1
Active
1
X
Active
相關(guān)PDF資料
PDF描述
ST16C654CQ64 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
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