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參數(shù)資料
| 型號： | ST16C552A |
| 廠商： | Exar Corporation |
| 英文描述： | Dual UART with 16-Byte FIFO and Parallel Printer Port(雙通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出和并行打印機(jī)端口）) |
| 中文描述： | 雙UART），16字節(jié)FIFO和并行打印機(jī)端口（雙通用異步接收器/發(fā)送器（帶16字節(jié)的先進(jìn)先出和并行打印機(jī)端口） |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 463K |
| 代理商： | ST16C552A |
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17
ST16C552/552A
Rev. 3.30
A2 A1 A0
Register
[Default]
Note 5*
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
Printer Port Register Set: Note 3*
[X]
0
0
PR[00]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
[X]
0
0
PR[00]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
[X]
0
1
SR[4F]
-Busy
-ACK
PE
SLCT
Error
State
-IRQ
logic
1
logic
1
[X]
0
1
IOSEL
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
[X]
1
0
COM[E0]
logic
1
logic
1
logic
1
-INTP
Enable
-SLCTIN
INIT
-Auto
FDXT
-STROBE
[X]
1
0
CON[00]
[X]
[X]
PD 0-7
IN/OUT
-INTP
Enable
-SLCTIN
INIT
-Auto
FDXT
-STROBE
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.
Note 5*
The value between the square brackets represents the registers initialized HEX value, X =N/A.
MODEM (UART) REGISTER DESCRIPTIONS
Transmit (THR) and Receive (RHR) Holding Reg-
isters
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = FIFO full, logic 1= at least
one FIFO location available).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the 552/552A and receive FIFO by
reading the RHR register. The receive section pro-
vides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal
receiver counter starts counting clocks at the 16x
clock rate. After 7 1/2 clocks the start bit time should
be shifted to the center of the start bit. At this time the
start bit is sampled and if it is still a logic 0 it is
validated. Evaluating the start bit in this manner
prevents the receiver from assembling a false charac-
ter. Receiver status codes will be posted in the LSR.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST16C552ACJ68 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C552ACJ68-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO&PARALELPRNTPORT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C552ACJ68TR-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO&PARALELPRNTPORT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| ST16C552AIJ68 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT |
| ST16C552AIJ68-F | 功能描述:UART 接口集成電路 DUAL UART W/16BYTE FIFO&PARALELPRNTPORT RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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