參數(shù)資料
型號: ST16C552A
廠商: Exar Corporation
英文描述: Dual UART with 16-Byte FIFO and Parallel Printer Port(雙通用異步接收器/發(fā)送器(帶16字節(jié)的先進先出和并行打印機端口))
中文描述: 雙UART),16字節(jié)FIFO和并行打印機端口(雙通用異步接收器/發(fā)送器(帶16字節(jié)的先進先出和并行打印機端口)
文件頁數(shù): 13/40頁
文件大?。?/td> 463K
代理商: ST16C552A
13
ST16C552/552A
Rev. 3.30
DMA Operation
The 552/552A FIFO trigger level provides additional
flexibility to the user for block mode operation. LSR
bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s). The user can
optionally operate the transmit and receive FIFOs in
the DMA mode (FCR bit-3). When the transmit and
receive FIFOs are enabled and the DMA mode is
deactivated (DMA Mode 0), the 552/552A activates
the interrupt output pin for each data transmit or
receive operation. When DMA mode is activated
(DMA Mode 1), the user takes the advantage of
block mode operation by loading or unloading the
FIFO in a block sequence determined by the receive
trigger level and the transmit FIFO. In this mode, the
552/552A sets the interrupt output pin when charac-
ters in the transmit FIFO is below 16, or the characters
in the receive FIFOs are above the receive trigger
level.
Power Down Mode
The 552 is designed to operate with low power con-
sumption. The 552 (only) is designed with a special
power down mode to further reduce power consump-
tion when the chip is not being used. When MCR bit-
7 and IER bit-5 are enabled (set to a logic 1), the 552
powers down. The use of two power down enable bits
helps to prevent accidental software shut-down. The
552 will remain powered down until disabled by setting
either IER bit-5 or MCR bit-7 to a logic 0.
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. MCR register bits 0-3 are used
for controlling loop-back diagnostic testing. In the
loop-back mode INT enable and MCR bit-2 in the MCR
register (bits 2,3) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 6). The -CTS, -DSR, -
CD, and -RI are disconnected from their normal
modem control inputs pins, and instead are connected
internally to -DTR, -RTS, INT enable and MCR bit-2.
Loop-back test data is entered into the transmit hold-
ing register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-
back connection. The receive UART converts the
serial data back into parallel data that is then made
available at the user data interface, D0-D7. The user
optionally compares the received data to the initial
transmitted data for verifying error free operation of
the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts
are fully operational. The Modem Control Interrupts
are also operational. However, the interrupts can only
be read using lower four bits of the Modem Control
Register (MCR bits 0-3) instead of the four Modem
Status Register bits 4-7. The interrupts are still con-
trolled by the IER.
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