參數(shù)資料
型號(hào): ST16C2552IJ44
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
中文描述: 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 4/28頁(yè)
文件大?。?/td> 121K
代理商: ST16C2552IJ44
3-138
ST16C2552
S
Symbol
Pin
Signal Type
Pin Description
SYMBOL DESCRIPTION
INT A/B
34,17
O
Interrupt output A/B. (active high) This pin goes high (when
enabled by the interrupt enable register) whenever a re-
ceiver error, receiver data available, transmitter empty, or
modem status condition flag is detected.
MF* A/B
35,19
O
OP2* (interrupt enable), BAUDOUT* and RXRDY* outputs.
These outputs are multiplexed via Alternate Function Reg-
ister. When output enable function is selected the MF* pin
stays high when INT out pin is set to three state mode and
goes low when INT pin is enabled. See bit-3 modem control
register (MCR bit-3). When BAUDOUT function is selected,
the 16 X TX/RX Baud rate clock output is generated.
RXRDY function can be selected to use to request a DMA
transfer of data from the Receive data FIFO. OP2* is the
default signal and it is selected immediately after master
reset or power-up.
TXRDY* A/B
1,32
O
Transmit ready. (active low) This pin goes high when the
transmit FIFO of the ST16C2552 is full. It can be used as a
single or multi-transfer.
RTS* A/B
36,23
O
Request to send A/B (active low). To indicate that the
transmitter has data ready to send. Writing a “1” in the
modem control register (MCR bit-1 ) will set this pin to a low
state. After the reset this pin will be set to high. Note that
this pin does not have any effect on the transmit or receive
operation.
DTR* A/B
37,27
O
Data terminal ready A/B (active low). To indicate that
ST16C2552 is ready to receive data. This pin can be
controlled via the modem control register (MCR bit-0).
Writing a “1” at the MCR bit-0 will set the DTR* output to low.
This pin will be set to high state after writing a “0” to that
register or after the reset . Note that this pin does not have
any effect on the transmit or receive operation.
RESET
21
I
Master reset. (active high) A high on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.
相關(guān)PDF資料
PDF描述
ST162552 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs
ST16C2552CJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ST16C2552IJ 2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
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