REV. 4.4.1 2.97V TO 5.5V DUART WITH 16-BYTE FIFO 2.4 Channel A and B Internal Registers Each UART channel in the C2550 has a standa" />
參數(shù)資料
型號： ST16C2550CQ-0A-EB
廠商： Exar Corporation
文件頁數(shù)： 37/37頁
文件大小： 0K
描述： EVAL BOARD FOR ST16C2550
標(biāo)準(zhǔn)包裝： 1
系列： *
ST16C2550
9
REV. 4.4.1
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
2.4
Channel A and B Internal Registers
Each UART channel in the C2550 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.5
DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the C2550 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show
their behavior. Also see Figures 17 through 22.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B
0 = 1 byte.
1 = no data.
0 = at least 1 byte in FIFO
1 = FIFO empty.
1 to 0 transition when FIFO reaches the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B
0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.6
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Tables 3and 4summarize the operating behavior for the transmitter and receiver. Also see Figures 17
through 22.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
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