![](http://datasheet.mmic.net.cn/370000/ST16C1450_datasheet_16733411/ST16C1450_21.png)
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REV. 4.2.0
ST16C1450/51
2.97V TO 5.5V UART
21
CTS#
(active high, logical 1). Normally this bit is the compliment of the CTS# input. In the loopback mode, this
bit is equivalent to bit-1 in the MCR register. The CTS# input may be used as a general purpose input when the
modem interface is not used.
MSR[5]: DSR Input Status
DSR#
(active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this
bit is equivalent to bit-0 in the MCR register. The DSR# input may be used as a general purpose input when the
modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is
equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the
modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the
modem interface is not used.
4.9
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
T
ABLE
6: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLL
Bits 7-0 = 0xXX
DLM
Bits 7-0 = 0xXX
RHR
Bits 7-0 = 0xXX
THR
Bits 7-0 = 0xXX
IER
Bits 7-0 = 0x00
ISR
Bits 7-0 = 0x01
LCR
Bits 7-0 = 0x00
MCR
Bits 7-0 = 0x00
LSR
Bits 7-0 = 0x60
MSR
Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR
Bits 7-0 = 0xFF
I/O SIGNALS
RESET STATE
TX
Logic 1
RTS#
Logic 1
DTR#
Logic 1
RST
Logic 1
INT
Three-State Condition