參數(shù)資料
型號： ST16654
廠商： Exar Corporation
英文描述： QUAD UART WITH 64-BYTE FIFO AND INFRARED (IrDA) ENCODER/DECODER
中文描述： 四UART的64字節(jié)FIFO和紅外線（IrDA）編碼/解碼器
文件頁數(shù)： 29/49頁
文件大?。?/td> 444K
代理商： ST16654
ST16C654/654D
5-93
Rev. 4.10
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity. (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, receiver checks the data and parity for transmis-
sion errors.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The
receiver must be programmed to check the same
format. (normal default condition)
Logic 1 = EVEN Parity
is generated by forcing an even
the number of logic 1’s in the transmitted. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
LCR BIT-5 = logic 0, parity is not forced. (normal
default condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive
data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive
data.
LCR
Bit-5
LCR
Bit-4
LCR
Bit-3
Parity selection
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
No parity
Odd parity
Even parity
Force parity “1”
Forced parity “0”
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break
condition.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default
condition)
Logic 1 = Divisor latch and enhanced feature register
enabled.
Modem Control Register (MCR)
This register controls the interface with the modem or
a peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal
default condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal
default condition)
Logic 1 = Force -RTS output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
MCR BIT-2:
This bit is used in the Loopback mode only. In the
loopback mode this bit is use to write the state of the
modem -RI interface signal via -OP1.
MCR BIT-3: (Used to control the modem -CD signal
in the loopback mode.)
Logic 0 = Forces INT (A-D) outputs to the three state
mode during the 16 mode. (normal default condition)
In the Loopback mode, sets -OP2 (-CD) internally to a
logic 1.
Logic 1 = Forces the INT (A-D) outputs to the active
mode during the 16 mode. In the Loopback mode, sets
-OP2 (-CD) internally to a logic 0.
MCR BIT-4:
Logic 0 = Disable loopback mode. (normal default
condition)
Logic 1 = Enable local loopback mode (diagnostics).
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